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authorVijay Kandiah <[email protected]>2021-10-17 02:07:39 -0500
committerGitHub <[email protected]>2021-10-17 02:07:39 -0500
commit4a4fc87a2dcd95bfe298f2b3d18a9833a506e499 (patch)
treef45fe00a86fb814ebf3f5e711674f233dcdb73a2 /src/gpgpu-sim/gpu-sim.cc
parent90ec3399763d7c8512cfe7dc193473086c38ca38 (diff)
parent84c4f46fb78b529ab2447d7a676f5b3ac2d9c05f (diff)
Merge pull request #5 from accel-sim/dev
GPGPU-Sim Latest Dev Integration
Diffstat (limited to 'src/gpgpu-sim/gpu-sim.cc')
-rw-r--r--src/gpgpu-sim/gpu-sim.cc11
1 files changed, 10 insertions, 1 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 1650688..56ede05 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -249,6 +249,8 @@ void shader_core_config::reg_options(class OptionParser *opp) {
" {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_"
"alloc>,<mshr>:<N>:<merge>,<mq> | none}",
"none");
+ option_parser_register(opp, "-gpgpu_l1_cache_write_ratio", OPT_UINT32,
+ &m_L1D_config.m_wr_percent, "L1D write ratio", "0");
option_parser_register(opp, "-gpgpu_l1_banks", OPT_UINT32,
&m_L1D_config.l1_banks, "The number of L1 cache banks",
"1");
@@ -326,7 +328,14 @@ void shader_core_config::reg_options(class OptionParser *opp) {
option_parser_register(
opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size,
"Size of shared memory per shader core (default 16kB)", "16384");
- option_parser_register(opp, "-gpgpu_adaptive_cache_config", OPT_UINT32,
+ option_parser_register(opp, "-gpgpu_shmem_option", OPT_CSTR,
+ &gpgpu_shmem_option,
+ "Option list of shared memory sizes", "0");
+ option_parser_register(
+ opp, "-gpgpu_unified_l1d_size", OPT_UINT32,
+ &m_L1D_config.m_unified_cache_size,
+ "Size of unified data cache(L1D + shared memory) in KB", "0");
+ option_parser_register(opp, "-gpgpu_adaptive_cache_config", OPT_BOOL,
&adaptive_cache_config, "adaptive_cache_config", "0");
option_parser_register(
opp, "-gpgpu_shmem_sizeDefault", OPT_UINT32, &gpgpu_shmem_sizeDefault,