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authortgrogers <[email protected]>2017-11-18 15:48:26 -0500
committertgrogers <[email protected]>2017-11-18 15:48:26 -0500
commit9233f6f9eeea537187deb64add77a320442aa621 (patch)
treec2351512f93d44354ea31509a2964d03fe530c71 /src/gpgpu-sim/gpu-sim.cc
parenta2b163e4476387df8693c1a784cf094f8868a086 (diff)
vectoradd is successfully filling the l2
Diffstat (limited to 'src/gpgpu-sim/gpu-sim.cc')
-rw-r--r--src/gpgpu-sim/gpu-sim.cc17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 11ac5df..263cbad 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -1595,6 +1595,23 @@ void shader_core_ctx::dump_warp_state( FILE *fout ) const
m_warp[w].print(fout);
}
+
+void gpgpu_sim::memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t count )
+{
+ assert (dst_start_addr % 32 == 0);
+ // Right now - I am just going to assume you write the whole last cache line...
+// assert (count % 128 == 0);
+ for ( unsigned counter = 0; counter < count; counter += 32 ) {
+ const size_t wr_addr = dst_start_addr + counter;
+ addrdec_t raw_addr;
+ mem_access_sector_mask_t mask;
+ mask.set(wr_addr % 128 / 32);
+ m_memory_config->m_address_mapping.addrdec_tlx( wr_addr, &raw_addr );
+ const unsigned partition_id = raw_addr.sub_partition / m_memory_config->m_n_sub_partition_per_memory_channel;
+ m_memory_partition_unit[ partition_id ]->handle_memcpy_to_gpu( wr_addr, raw_addr.sub_partition, mask );
+ }
+}
+
void gpgpu_sim::dump_pipeline( int mask, int s, int m ) const
{
/*