diff options
| author | JRPan <[email protected]> | 2025-05-14 16:34:10 -0700 |
|---|---|---|
| committer | GitHub <[email protected]> | 2025-05-14 23:34:10 +0000 |
| commit | bc268aabf96d99f12ba3bfbf233c8b40225a95a9 (patch) | |
| tree | bebe7298f6e136646247f2805ff1457e490e8434 /src/gpgpu-sim/gpu-sim.cc | |
| parent | c30043e28dcf3fe4da4973ec3ee461f93a7c4a01 (diff) | |
Performance improvements (#67)
* performance inprovements
* use node_id before incremented
* Cleanup iSLIP
* run set_dram_power_stats only when power model enabled
---------
Co-authored-by: WilliamMTK <[email protected]>
Diffstat (limited to 'src/gpgpu-sim/gpu-sim.cc')
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 3f84d42..9055502 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -2012,16 +2012,18 @@ void gpgpu_sim::cycle() { m_memory_partition_unit[i] ->dram_cycle(); // Issue the dram command (scheduler + delay model) // Update performance counters for DRAM - m_memory_partition_unit[i]->set_dram_power_stats( - m_power_stats->pwr_mem_stat->n_cmd[CURRENT_STAT_IDX][i], - m_power_stats->pwr_mem_stat->n_activity[CURRENT_STAT_IDX][i], - m_power_stats->pwr_mem_stat->n_nop[CURRENT_STAT_IDX][i], - m_power_stats->pwr_mem_stat->n_act[CURRENT_STAT_IDX][i], - m_power_stats->pwr_mem_stat->n_pre[CURRENT_STAT_IDX][i], - m_power_stats->pwr_mem_stat->n_rd[CURRENT_STAT_IDX][i], - m_power_stats->pwr_mem_stat->n_wr[CURRENT_STAT_IDX][i], - m_power_stats->pwr_mem_stat->n_wr_WB[CURRENT_STAT_IDX][i], - m_power_stats->pwr_mem_stat->n_req[CURRENT_STAT_IDX][i]); + if (m_config.g_power_simulation_enabled) { + m_memory_partition_unit[i]->set_dram_power_stats( + m_power_stats->pwr_mem_stat->n_cmd[CURRENT_STAT_IDX][i], + m_power_stats->pwr_mem_stat->n_activity[CURRENT_STAT_IDX][i], + m_power_stats->pwr_mem_stat->n_nop[CURRENT_STAT_IDX][i], + m_power_stats->pwr_mem_stat->n_act[CURRENT_STAT_IDX][i], + m_power_stats->pwr_mem_stat->n_pre[CURRENT_STAT_IDX][i], + m_power_stats->pwr_mem_stat->n_rd[CURRENT_STAT_IDX][i], + m_power_stats->pwr_mem_stat->n_wr[CURRENT_STAT_IDX][i], + m_power_stats->pwr_mem_stat->n_wr_WB[CURRENT_STAT_IDX][i], + m_power_stats->pwr_mem_stat->n_req[CURRENT_STAT_IDX][i]); + } } } |