diff options
| author | Tor Aamodt <[email protected]> | 2010-10-21 07:16:49 -0800 |
|---|---|---|
| committer | Tor Aamodt <[email protected]> | 2010-10-21 07:16:49 -0800 |
| commit | dc93f319051a9a9936a02cd9c1f7843a382a2da0 (patch) | |
| tree | 6c042ccab67be43b8fe442ab435ffbfd0f34e56e /src/gpgpu-sim/gpu-sim.cc | |
| parent | ee5ea34857e4ecc6c63d4971e549076c6a9888ba (diff) | |
1. rewriting memory access generation code (from scratch), why not...
passing CUDA 3.1 and ptxplus correlation, but correlation still bad (0.62)...
after debugging 1 to get it working with ptxplus, problem is very clear:
shared and constant cache accesses not occuring for operations that combine these with ALU operations.
TODO:
have a "read-operands" stage, which somehow combines operand collector
register reading with shared and const memory accesses...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7895]
Diffstat (limited to 'src/gpgpu-sim/gpu-sim.cc')
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index e3e54dc..a7b2ecf 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -259,8 +259,8 @@ void gpgpu_sim::reg_options(option_parser_t opp) "Size of shared memory per shader core (default 16kB)", "16384"); - option_parser_register(opp, "-gpgpu_shmem_pipe_speedup", OPT_INT32, &m_shader_config->gpgpu_shmem_pipe_speedup, - "Number of groups each warp is divided for shared memory bank conflict check", + option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &m_shader_config->shmem_warp_parts, + "Number of portions a warp is divided into for shared memory bank conflict check ", "2"); option_parser_register(opp, "-gpgpu_deadlock_detect", OPT_BOOL, &gpu_deadlock_detect, @@ -431,7 +431,7 @@ void gpgpu_sim::init_gpu() sscanf(gpgpu_runtime_stat, "%d:%x", &gpu_stat_sample_freq, &gpu_runtime_stat_flag); m_shader_config->pdom_sched_type = m_pdom_sched_type; - m_shader_config->gpgpu_n_shmem_bank=16; + m_shader_config->num_shmem_bank=16; m_cluster = new simt_core_cluster*[m_shader_config->n_simt_clusters]; for (unsigned i=0;i<m_shader_config->n_simt_clusters;i++) |