diff options
| author | Mahmoud <[email protected]> | 2018-09-07 22:01:31 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2018-09-07 22:01:31 -0400 |
| commit | f852a7108e691045dd3910065836a817babcde8c (patch) | |
| tree | 16a83744048f5c2bd43dff818187786372047f00 /src/gpgpu-sim/gpu-sim.cc | |
| parent | b013499f5f490086c7a7c5c28b04346e79ab2635 (diff) | |
adding streamin cache + fixing TEX cache + adding l1 latency and smem latency
Diffstat (limited to 'src/gpgpu-sim/gpu-sim.cc')
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index ea2dfba..08d4525 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -250,6 +250,12 @@ void shader_core_config::reg_options(class OptionParser * opp) "per-shader L1 data cache config " " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}", "none" ); + option_parser_register(opp, "-l1_latency", OPT_UINT32, &m_L1D_config.l1_latency, + "L1 Hit Latency", + "0"); + option_parser_register(opp, "-smem_latency", OPT_UINT32, &smem_latency, + "smem Latency", + "3"); option_parser_register(opp, "-gpgpu_cache:dl1PrefL1", OPT_CSTR, &m_L1D_config.m_config_stringPrefL1, "per-shader L1 data cache config " " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}", |