Fixing L2 WriteBack bug caused by using the partition address for both set index generation and storing tag/block address.

- Added l2_cache_config class to extend the baseline
- Allow custom set_index per cache. Modified L2 set_index function to use the memory partition address
- Modified the cache tag to now be tag+set_index (same as the block address). Useful for more complex set index generation functions that can allow different indexes to map to the same set.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15182]

1 files changed, 2 insertions, 2 deletions

diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index c04c1c1..6e5c3f0 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -202,14 +202,14 @@ struct memory_config {
       tWTP = (WL+(BL/data_command_freq_ratio)+tWR);
       dram_atom_size = BL * busW * gpu_n_mem_per_ctrlr; // burst length x bus width x # chips per partition 
       m_address_mapping.init(m_n_mem);
-      m_L2_config.init();
+      m_L2_config.init(&m_address_mapping);
       m_valid = true;
       icnt_flit_size = 32; // Default 32
    }
    void reg_options(class OptionParser * opp);
 
    bool m_valid;
-   cache_config m_L2_config;
+   l2_cache_config m_L2_config;
    bool m_L2_texure_only;
 
    char *gpgpu_dram_timing_opt;