diff options
| author | Tor Aamodt <[email protected]> | 2010-10-24 23:41:43 -0800 |
|---|---|---|
| committer | Tor Aamodt <[email protected]> | 2010-10-24 23:41:43 -0800 |
| commit | 0efd3c00f5611bfa82b01d87d175122388d621cc (patch) | |
| tree | b86c29b46a2bdf1586dd1d321e760c71df841d3f /src/gpgpu-sim/l2cache.cc | |
| parent | 826a0dc10ca939af1f2c24d0d2e63eb2b33cb731 (diff) | |
0.9756 correlation. Set L1T line size to 128 bytes... problem was
stalling to send four requests per warp into L1T tag lookup.
If L1T is really 32B blocks (as per Henry's paper), this suggests
banking of L1T needs to be modeled.
Other changes:
1. bug fix in memory access generation for texture/const cache access
2. adding back memory latency measurement for visualizer
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]
Diffstat (limited to 'src/gpgpu-sim/l2cache.cc')
| -rw-r--r-- | src/gpgpu-sim/l2cache.cc | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index 14f1f12..45b8eef 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -216,6 +216,16 @@ void memory_stats_t::print( FILE *fp ) fprintf(fp,"L2_read_hit = %d\n", L2_read_hit); } +void memory_stats_t::visualizer_print( gzFile visualizer_file ) +{ + gzprintf(visualizer_file, "Ltwowritemiss: %d\n", L2_write_miss); + gzprintf(visualizer_file, "Ltwowritehit: %d\n", L2_write_hit); + gzprintf(visualizer_file, "Ltworeadmiss: %d\n", L2_read_miss); + gzprintf(visualizer_file, "Ltworeadhit: %d\n", L2_read_hit); + if (num_mfs) + gzprintf(visualizer_file, "averagemflatency: %lld\n", mf_total_lat/num_mfs); +} + void gpgpu_sim::L2c_print_cache_stat() const { unsigned i, j, k; |