Merging Power model into Fermi

//depot/gpgpu_sim_research/fermi_power/distribution/...

to //depot/gpgpu_sim_research/fermi/distribution/...

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]

1 files changed, 86 insertions, 10 deletions

diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc
index c03c47f..281da7f 100644
--- a/src/gpgpu-sim/l2cache.cc
+++ b/src/gpgpu-sim/l2cache.cc
@@ -109,6 +109,7 @@ void memory_partition_unit::cache_cycle( unsigned cycle )
 				mf->set_reply();
 				mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
 				m_L2_icnt_queue->push(mf);
+				n_mem_to_simt+=mf->get_num_flits(false); // Interconnect power stats (# of flits sent to the SMs)
            }else{
 				m_request_tracker.erase(mf);
 				delete mf;
@@ -127,6 +128,7 @@ void memory_partition_unit::cache_cycle( unsigned cycle )
             mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
             m_L2_icnt_queue->push(mf);
             m_dram_L2_queue->pop();
+            n_mem_to_simt+=mf->get_num_flits(false); // Interconnect power stats (# of flits sent to the SMs)
         }
     }
 
@@ -158,6 +160,7 @@ void memory_partition_unit::cache_cycle( unsigned cycle )
                             mf->set_reply();
                             mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
                             m_L2_icnt_queue->push(mf);
+                            n_mem_to_simt+=mf->get_num_flits(false); // Interconnect power stats (# of flits sent to the SMs)
                         }
                         m_icnt_L2_queue->pop();
                     } else {
@@ -221,24 +224,75 @@ void memory_partition_unit::print( FILE *fp ) const
 
 void memory_stats_t::print( FILE *fp )
 {
-    fprintf(fp,"L2_write_miss = %d\n", L2_write_miss);
-    fprintf(fp,"L2_write_hit = %d\n", L2_write_hit);
-    fprintf(fp,"L2_read_miss = %d\n", L2_read_miss);
-    fprintf(fp,"L2_read_hit = %d\n", L2_read_hit);
+
+    fprintf(fp,"gpgpu_l2_write_miss = %d\n", L2_write_miss);
+    fprintf(fp,"gpgpu_l2_write_access = %d\n", L2_write_access);
+    fprintf(fp,"gpgpu_l2_read_miss = %d\n", L2_read_miss);
+    fprintf(fp,"gpgpu_l2_read_access = %d\n", L2_read_access);
+
 }
 
 void memory_stats_t::visualizer_print( gzFile visualizer_file )
 {
    gzprintf(visualizer_file, "Ltwowritemiss: %d\n", L2_write_miss);
-   gzprintf(visualizer_file, "Ltwowritehit: %d\n",  L2_write_hit);
+   gzprintf(visualizer_file, "Ltwowritehit: %d\n",  L2_write_access-L2_write_miss);
    gzprintf(visualizer_file, "Ltworeadmiss: %d\n", L2_read_miss);
-   gzprintf(visualizer_file, "Ltworeadhit: %d\n", L2_read_hit);
-   signed long long average_mf_latency = 0; 
-   if (mf_num_lat_pw) 
-      average_mf_latency = mf_tot_lat_pw / mf_num_lat_pw; 
-   gzprintf(visualizer_file, "averagemflatency: %lld\n", average_mf_latency);
+   gzprintf(visualizer_file, "Ltworeadhit: %d\n", L2_read_access-L2_read_miss);
+   if (num_mfs)
+      gzprintf(visualizer_file, "averagemflatency: %lld\n", mf_total_lat/num_mfs);
 }
 
+void gpgpu_sim::print_dram_L2_stats(FILE *fout) const
+{
+
+	unsigned cmd=0;
+	unsigned activity=0;
+	unsigned nop=0;
+	unsigned act=0;
+	unsigned pre=0;
+	unsigned rd=0;
+	unsigned wr=0;
+	unsigned req=0;
+	unsigned l2_read_access=0;
+	unsigned l2_read_miss=0;
+	unsigned l2_write_access=0;
+	unsigned l2_write_miss=0;
+	unsigned tot_cmd=0;
+	unsigned tot_nop=0;
+	unsigned tot_act=0;
+	unsigned tot_pre=0;
+	unsigned tot_rd=0;
+	unsigned tot_wr=0;
+	unsigned tot_req=0;
+	unsigned tot_l2_read_access=0;
+	unsigned tot_l2_read_miss=0;
+	unsigned tot_l2_write_access=0;
+	unsigned tot_l2_write_miss=0;
+
+	for (unsigned i=0;i<m_memory_config->m_n_mem;i++){
+		m_memory_partition_unit[i]->set_dram_power_stats(cmd,activity,nop,act,pre,rd,wr,req);
+		m_memory_partition_unit[i]->set_L2cache_power_stats(l2_read_access,l2_read_miss,l2_write_access,l2_write_miss);
+		tot_cmd+=cmd;
+		tot_nop+=nop;
+		tot_act+=act;
+		tot_pre+=pre;
+		tot_rd+=rd;
+		tot_wr+=wr;
+		tot_req+=req;
+		tot_l2_read_access+=l2_read_access;
+		tot_l2_read_miss+=l2_read_miss;
+		tot_l2_write_access+=l2_write_access;
+		tot_l2_write_miss+=l2_write_miss;
+	}
+	fprintf(fout,"gpgpu_n_l2_cache_read_access = %d\n",tot_l2_read_access );
+	fprintf(fout,"gpgpu_n_l2_cache_read_miss = %d\n",tot_l2_read_miss );
+	fprintf(fout,"gpgpu_n_l2_cache_write_access = %d\n",tot_l2_write_access );
+	fprintf(fout,"gpgpu_n_l2_cache_write_miss = %d\n",tot_l2_write_miss );
+    fprintf(fout,"gpgpu_n_dram_reads = %d\n",tot_rd );
+    fprintf(fout,"gpgpu_n_dram_writes = %d\n",tot_wr );
+    fprintf(fout,"gpgpu_n_dram_activate = %d\n",tot_act );
+
+}
 void gpgpu_sim::L2c_print_cache_stat() const
 {
     unsigned i, j, k;
@@ -341,3 +395,25 @@ void memory_partition_unit::dram_cycle()
         m_dram->push(mf);
     }
 }
+
+void memory_partition_unit::set_dram_power_stats(unsigned &n_cmd,
+												unsigned &n_activity,
+												unsigned &n_nop,
+												unsigned &n_act,
+												unsigned &n_pre,
+												unsigned &n_rd,
+												unsigned &n_wr,
+												unsigned &n_req) const{
+	m_dram->set_dram_power_stats(n_cmd, n_activity, n_nop, n_act, n_pre, n_rd, n_wr, n_req);
+}
+
+void memory_partition_unit::set_L2cache_power_stats(unsigned &n_read_access,
+												unsigned &n_read_miss,
+												unsigned &n_write_access,
+												unsigned &n_write_miss) const{
+	m_L2cache->get_data_stats(n_read_access,n_read_miss,n_write_access,n_write_miss);
+}
+
+void memory_partition_unit::set_icnt_power_stats(unsigned &mem_to_simt) const{
+	mem_to_simt = n_mem_to_simt;
+}