Modified the cache hierarchy, reorganized code to eliminate code replication, implemented write allocate / write back policies in L2 cache, added configurable parameters in gpgpusim.config ("W" = Write Allocate, "N" = No write allocate -> "P" = Private, "S" = shared), modified the cache configuration lines to always be separated by ":" instead of ":" and ",", and modified L1 and L2 data cache to be "Write Back" caches instead of "Read Only".

Still need to implement Ahmed's sectored cache implementation.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14081]

1 files changed, 8 insertions, 3 deletions

diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc
index a252c84..a580052 100644
--- a/src/gpgpu-sim/l2cache.cc
+++ b/src/gpgpu-sim/l2cache.cc
@@ -105,9 +105,14 @@ void memory_partition_unit::cache_cycle( unsigned cycle )
     if( !m_config->m_L2_config.disabled()) {
        if ( m_L2cache->access_ready() && !m_L2_icnt_queue->full() ) {
            mem_fetch *mf = m_L2cache->next_access();
-           mf->set_reply();
-           mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
-           m_L2_icnt_queue->push(mf);
+           if(mf->get_access_type() != L2_WR_ALLOC_R){ // Don't pass write allocate read request back to upper level cache
+				mf->set_reply();
+				mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
+				m_L2_icnt_queue->push(mf);
+           }else{
+				m_request_tracker.erase(mf);
+				delete mf;
+           }
        }
     }