diff options
| author | Mahmoud <[email protected]> | 2019-08-23 12:26:46 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2019-08-23 12:26:46 -0400 |
| commit | bd14ce38470dfc54c690db09f00ee5c18b577575 (patch) | |
| tree | fa8a36c5c831fedcacd2632cb8efd5fec2a83b92 /src/gpgpu-sim/l2cache.cc | |
| parent | f946986a2337df4cd96ac6ec0956ac25644fa1a9 (diff) | |
fixing CUDA 10 fail
Diffstat (limited to 'src/gpgpu-sim/l2cache.cc')
| -rw-r--r-- | src/gpgpu-sim/l2cache.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index f1672f9..39a5812 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -257,7 +257,7 @@ void memory_partition_unit::simple_dram_model_cycle() d.req = mf; d.ready_cycle = m_gpu->gpu_sim_cycle+m_gpu->gpu_tot_sim_cycle + m_config->dram_latency; m_dram_latency_queue.push_back(d); - mf->set_status(IN_PARTITION_DRAM_LATENCY_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); + mf->set_status(IN_PARTITION_DRAM_LATENCY_QUEUE,m_gpu->gpu_sim_cycle+m_gpu->gpu_tot_sim_cycle); m_arbitration_metadata.borrow_credit(spid); break; // the DRAM should only accept one request per cycle } |