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authorTor Aamodt <[email protected]>2010-10-10 21:19:52 -0800
committerTor Aamodt <[email protected]>2010-10-10 21:19:52 -0800
commitb3ce70a797756285ea9b15b3e5cf515d8b6a2b63 (patch)
tree5b84d880e646f80611cc5b01931fdde622c5e06c /src/gpgpu-sim/mem_fetch.cc
parent0151c5c566dcbcbb962acf35c86a8e0f4a4a6eb6 (diff)
1. create function unit classes for SP, SFU, LD/ST.
2. refactor memory stage into a ld/st function unit 3. refactor memory access generation (moved into warp_inst_t class) the above should make supporting fermi uarch much easier passing CUDA 3.1 regression still need to... (a) update scoreboard to keep count of outstanding memory requests and use operand collector for writebacks into register file (b) add back shared memory pipeline delay (c) remove use of MSHR's for non-cached global/local accesses (d) replace texture cache with a split tag/data array pipe (e) re-implement memory_partition stuff so it makes more sense [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7844]
Diffstat (limited to 'src/gpgpu-sim/mem_fetch.cc')
-rw-r--r--src/gpgpu-sim/mem_fetch.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc
index e2bc3e3..1a4af1e 100644
--- a/src/gpgpu-sim/mem_fetch.cc
+++ b/src/gpgpu-sim/mem_fetch.cc
@@ -107,7 +107,7 @@ void mem_fetch::print( FILE *fp ) const
{
fprintf(fp," mf: uid=%6u, addr=0x%08llx, sid=%u, wid=%u, pc=0x%04x, %s, bank=%u, ",
request_uid, addr, sid, wid, pc, (m_write?"write":"read "), tlx.bk);
- if( mshr ) mshr->print(fp,0x100);
+ if( mshr ) mshr->print(fp);
else fprintf(fp,"\n");
}