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authorTayler Hetherington <[email protected]>2013-06-16 12:26:07 -0800
committerAndrew Boktor <[email protected]>2014-08-14 13:50:47 -0700
commitb90f5f6d42e91fe5e093ed2656c1b64fc3257469 (patch)
treea76344609d30978528796dadbb198226b4c8a53b /src/gpgpu-sim/mem_latency_stat.cc
parent821753ac64ac2b3f4a441d0ed6d8bb0cdffb0fb8 (diff)
Review: 33001. Updating/cleaning up the cache statistics. Moving the statistics from the tag array to the cache access functions. Added cache_stats class to record all memory accesses and access outcomes to each cache. Removed L2CacheAccessBreakdown_t. Cleaned up power_stats to reflect changes in the cache stats. Updated the cache stats printing. This will cause the performance gold files to change as the output format has been changed.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16452]
Diffstat (limited to 'src/gpgpu-sim/mem_latency_stat.cc')
-rw-r--r--src/gpgpu-sim/mem_latency_stat.cc4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc
index a2c4177..fde0eff 100644
--- a/src/gpgpu-sim/mem_latency_stat.cc
+++ b/src/gpgpu-sim/mem_latency_stat.cc
@@ -125,10 +125,6 @@ memory_stats_t::memory_stats_t( unsigned n_shader, const struct shader_core_conf
}
}
- // L2_write_miss=0;
- // L2_write_access=0;
- // L2_read_access=0;
- // L2_read_miss=0;
L2_cbtoL2length = (unsigned int*) calloc(mem_config->m_n_mem, sizeof(unsigned int));
L2_cbtoL2writelength = (unsigned int*) calloc(mem_config->m_n_mem, sizeof(unsigned int));
L2_L2tocblength = (unsigned int*) calloc(mem_config->m_n_mem, sizeof(unsigned int));