diff options
| author | Tor Aamodt <[email protected]> | 2010-10-24 23:41:43 -0800 |
|---|---|---|
| committer | Tor Aamodt <[email protected]> | 2010-10-24 23:41:43 -0800 |
| commit | 0efd3c00f5611bfa82b01d87d175122388d621cc (patch) | |
| tree | b86c29b46a2bdf1586dd1d321e760c71df841d3f /src/gpgpu-sim/mem_latency_stat.h | |
| parent | 826a0dc10ca939af1f2c24d0d2e63eb2b33cb731 (diff) | |
0.9756 correlation. Set L1T line size to 128 bytes... problem was
stalling to send four requests per warp into L1T tag lookup.
If L1T is really 32B blocks (as per Henry's paper), this suggests
banking of L1T needs to be modeled.
Other changes:
1. bug fix in memory access generation for texture/const cache access
2. adding back memory latency measurement for visualizer
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]
Diffstat (limited to 'src/gpgpu-sim/mem_latency_stat.h')
| -rw-r--r-- | src/gpgpu-sim/mem_latency_stat.h | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h index b7e4b64..87da046 100644 --- a/src/gpgpu-sim/mem_latency_stat.h +++ b/src/gpgpu-sim/mem_latency_stat.h @@ -69,6 +69,7 @@ #define MEM_LATENCY_STAT_H #include <stdio.h> +#include <zlib.h> class memory_stats_t { public: @@ -76,14 +77,15 @@ public: const struct shader_core_config *shader_config, const struct memory_config *mem_config ); - unsigned memlatstat_done( class mem_fetch *mf, unsigned n_warp_per_shader ); - void memlatstat_read_done( class mem_fetch *mf, unsigned n_warp_per_shader); + unsigned memlatstat_done( class mem_fetch *mf ); + void memlatstat_read_done( class mem_fetch *mf ); void memlatstat_dram_access( class mem_fetch *mf ); void memlatstat_icnt2mem_pop( class mem_fetch *mf); - void memlatstat_lat_pw( unsigned n_shader, unsigned n_thread_per_shader, unsigned warp_size ); + void memlatstat_lat_pw(); void memlatstat_print(unsigned n_mem, unsigned gpu_mem_n_bk); void print( FILE *fp ); + void visualizer_print( gzFile visualizer_file ); unsigned m_n_shader; @@ -115,10 +117,6 @@ public: unsigned int **totalbankaccesses; //bankaccesses[dram chip id][bank id] unsigned int *num_MCBs_accessed; //tracks how many memory controllers are accessed whenever any thread in a warp misses in cache unsigned int *position_of_mrq_chosen; //position of mrq in m_queue chosen - unsigned *mf_num_lat_pw_perwarp; - unsigned *mf_tot_lat_pw_perwarp; //total latency summed up per window per warp. divide by mf_num_lat_pw_perwarp to obtain average latency Per Window - unsigned long long int *mf_total_lat_perwarp; - unsigned *num_mfs_perwarp; unsigned ***mem_access_type_stats; // dram access type classification |
