Re-designed cache model:

- read only cache model with integrated mshrs (no L1D, yet); new
  cache interface should be easily extendable to support texture 
  cache with latency fifo and separate tag/data arrays, though
  this is not yet added (currently tags and data arrays are not
  decoupled for texture)
- new partition model using the above

removes all old MSHRs, L1D etc...

passing CUDA 3.1 regression

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7875]

1 files changed, 2 insertions, 5 deletions

diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h
index 14868ef..b7e4b64 100644
--- a/src/gpgpu-sim/mem_latency_stat.h
+++ b/src/gpgpu-sim/mem_latency_stat.h
@@ -73,8 +73,8 @@
 class memory_stats_t {
 public:
    memory_stats_t( unsigned n_shader, 
-                   struct shader_core_config *shader_config, 
-                   struct memory_config *mem_config );
+                   const struct shader_core_config *shader_config, 
+                   const struct memory_config *mem_config );
 
    unsigned memlatstat_done( class mem_fetch *mf, unsigned n_warp_per_shader );
    void memlatstat_read_done( class mem_fetch *mf, unsigned n_warp_per_shader);
@@ -83,8 +83,6 @@ public:
    void memlatstat_lat_pw( unsigned n_shader, unsigned n_thread_per_shader, unsigned warp_size );
    void memlatstat_print(unsigned n_mem, unsigned gpu_mem_n_bk);
 
-   void L2c_print_stat(unsigned n_mem);
-
    void print( FILE *fp );
 
    unsigned m_n_shader;
@@ -121,7 +119,6 @@ public:
    unsigned *mf_tot_lat_pw_perwarp; //total latency summed up per window per warp. divide by mf_num_lat_pw_perwarp to obtain average latency Per Window
    unsigned long long int *mf_total_lat_perwarp;
    unsigned *num_mfs_perwarp;
-   unsigned *acc_mrq_length;
    
    unsigned ***mem_access_type_stats; // dram access type classification