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authorTim Rogers <[email protected]>2019-06-19 10:33:43 -0400
committerGitHub <[email protected]>2019-06-19 10:33:43 -0400
commita1e2c4273542ca78098c9f4f25eebc087e0aec37 (patch)
tree2edd1e7c751b32fe75e392e6a595a0c99ff8b52f /src/gpgpu-sim/mem_latency_stat.h
parentaaf29157d28fd5ee9ebdafb86338a28df73e3baf (diff)
parent1a0dbc16e1a1959741385345b2bce38fb89c8695 (diff)
Merge pull request #96 from CoffeeBeforeArch/AerialVision_cache_support
AerialVision L2 Cache Support
Diffstat (limited to 'src/gpgpu-sim/mem_latency_stat.h')
-rw-r--r--src/gpgpu-sim/mem_latency_stat.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h
index 5b89202..982b9ae 100644
--- a/src/gpgpu-sim/mem_latency_stat.h
+++ b/src/gpgpu-sim/mem_latency_stat.h
@@ -47,6 +47,9 @@ public:
void visualizer_print( gzFile visualizer_file );
+ // Reset local L2 stats that are aggregated each sampling window
+ void clear_L2_stats_pw();
+
unsigned m_n_shader;
const struct shader_core_config *m_shader_config;
@@ -84,6 +87,11 @@ public:
unsigned ***mem_access_type_stats; // dram access type classification
+ // AerialVision L2 stats
+ unsigned L2_read_miss;
+ unsigned L2_write_miss;
+ unsigned L2_read_hit;
+ unsigned L2_write_hit;
// L2 cache stats
unsigned int *L2_cbtoL2length;