1. adding simt_core_cluster, which models a TPC or (for fermi) GPC...

   this gives us a place to stick caches shared among shader cores but
   on the shader side of the interconnect... maybe move the clock
   boundary code here? after integrating booksim 2 code?
2. added a pending write table to ldst_unit rather than scoreboard
   ... rationale is that ld/st unit needs to process register writes
   once it is done it can notify scoreboard once.
3. re-enabled shared memory delay (use pipeline within ldst_unit)
4. re-enabling operand collector writeback for all instruction types
5. disable MSHRs in this change list 

passing CUDA 3.1 regression

next? texture cache, then redo mshrs?

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]

1 files changed, 6 insertions, 7 deletions

diff --git a/src/gpgpu-sim/scoreboard.h b/src/gpgpu-sim/scoreboard.h
index 4e1c154..1b7235d 100644
--- a/src/gpgpu-sim/scoreboard.h
+++ b/src/gpgpu-sim/scoreboard.h
@@ -20,22 +20,21 @@ class Scoreboard {
 public:
     Scoreboard( unsigned sid, unsigned n_warps );
 
-    void printContents();
-
-    void reserveRegisters(unsigned wid, const inst_t *inst);
+    void reserveRegisters(const warp_inst_t *inst);
     void releaseRegisters(const warp_inst_t *inst);
+    void releaseRegister(unsigned wid, unsigned regnum);
 
-    bool checkCollision(unsigned wid, const inst_t *inst);
+    bool checkCollision(unsigned wid, const inst_t *inst) const;
     bool pendingWrites(unsigned wid) const;
+    void printContents() const;
 private:
     void reserveRegister(unsigned wid, unsigned regnum);
-    void releaseRegister(unsigned wid, unsigned regnum);
 
     unsigned m_sid;
 
     // keeps track of pending writes to registers
-    // indexed by warp id
-    std::vector< std::set<int> > reg_table;
+    // indexed by warp id, reg_id => pending write count
+    std::vector< std::set<unsigned> > reg_table;
 };