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| author | Mahmoud Khairy A. Abdallah <[email protected]> | 2020-02-13 12:32:39 -0500 |
|---|---|---|
| committer | Mahmoud Khairy A. Abdallah <[email protected]> | 2020-02-13 12:32:39 -0500 |
| commit | 5221ed98c5a7f0ceec3eb96216f4449635a74b22 (patch) | |
| tree | 695ec447a80d04870f0ba4e610b4004628de9f25 /src/gpgpu-sim/shader.cc | |
| parent | 1d3ccd32e70c6a6c524abbe8ff0ac450481290d4 (diff) | |
fixing pascal
Diffstat (limited to 'src/gpgpu-sim/shader.cc')
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 23050d3..7fc31f3 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -106,7 +106,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, } if(m_config->sub_core_model) { //in subcore model, each scheduler should has its own issue register, so num scheduler = reg width - assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_SP].get_size() ); + //assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_SP].get_size() ); assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_SFU].get_size() ); assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_MEM].get_size() ); if(m_config->gpgpu_tensor_core_avail) |