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authorAkshay Jain <[email protected]>2018-03-22 04:40:44 -0400
committerAkshay Jain <[email protected]>2018-03-22 04:40:44 -0400
commit525f177a1d4f1fc309d22197bc8af26ee8d4c454 (patch)
tree306f7f63d8d3bee9b4a0aab738dff1d274d898f3 /src/gpgpu-sim/shader.cc
parent0241bdee08d2bdf95b7f6f9518403c22f8f0bc53 (diff)
Change 283 by jain156@akshayj-lt1 on 2017/07/03 19:52:55
Adding the global load and store divergence statistics. The previous histogram has been modified to look at all memory requests, but that is not meaningful - so it can as well be removed.
Diffstat (limited to 'src/gpgpu-sim/shader.cc')
-rw-r--r--src/gpgpu-sim/shader.cc15
1 files changed, 13 insertions, 2 deletions
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index e7204c8..db6a532 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -441,6 +441,12 @@ void shader_core_stats::print( FILE* fout ) const
fprintf(fout,"gpgpu_mem_divergence_hist ");
gpgpu_mem_divergence_hist->fprint(fout);
fprintf(fout,"\n");
+ fprintf(fout,"gpgpu_gmem_ld_divergence_hist ");
+ gpgpu_gmem_ld_divergence_hist->fprint(fout);
+ fprintf(fout,"\n");
+ fprintf(fout,"gpgpu_gmem_st_divergence_hist ");
+ gpgpu_gmem_st_divergence_hist->fprint(fout);
+ fprintf(fout,"\n");
fprintf(fout, "gpgpu_n_load_insn = %d\n", gpgpu_n_load_insn);
fprintf(fout, "gpgpu_n_store_insn = %d\n", gpgpu_n_store_insn);
@@ -746,12 +752,17 @@ void shader_core_ctx::func_exec_inst( warp_inst_t &inst )
{
unsigned starting_queue_size;
execute_warp_inst_t(inst);
- if( inst.is_load() || inst.is_store() )
+ if( inst.is_load() || inst.is_store() ) {
starting_queue_size = inst.accessq_count();
inst.generate_mem_accesses();
if ( inst.space.get_type() == global_space ) {
- m_stats->gpgpu_mem_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size);
+ if (inst.is_load())
+ m_stats->gpgpu_gmem_ld_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size);
+ else if (inst.is_store())
+ m_stats->gpgpu_gmem_st_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size);
}
+ m_stats->gpgpu_mem_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size);
+ }
}
void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* next_inst, const active_mask_t &active_mask, unsigned warp_id )