diff options
| author | Mahmoud <[email protected]> | 2019-05-08 11:37:32 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2019-05-08 11:37:32 -0400 |
| commit | 5325856b19fbb175d1f2af0a48cc0fa8e453ca24 (patch) | |
| tree | f423fc04ce1aa3d0dc4011273986b4340d9f4ef8 /src/gpgpu-sim/shader.cc | |
| parent | fe6506a14839b8614b5f4daa2d8331441feb6902 (diff) | |
| parent | 90755c4dbdd8295b70632bb8e8868a980c9fd9ab (diff) | |
Merge branch 'dev' into dev-private
Diffstat (limited to 'src/gpgpu-sim/shader.cc')
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 16 |
1 files changed, 4 insertions, 12 deletions
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 09be1f6..007ad42 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1896,7 +1896,7 @@ void tensor_core::issue( register_set& source_reg ) unsigned pipelined_simd_unit::get_active_lanes_in_pipeline(){ active_mask_t active_lanes; active_lanes.reset(); - if(!m_config->fast_execution_mode || active_insts_in_pipeline){ + if(m_core->get_gpu()->get_config().g_power_simulation_enabled){ for( unsigned stage=0; (stage+1)<m_pipeline_depth; stage++ ){ if( !m_pipeline_reg[stage]->empty() ) active_lanes|=m_pipeline_reg[stage]->get_active_mask(); @@ -2014,7 +2014,7 @@ void pipelined_simd_unit::cycle() assert(active_insts_in_pipeline > 0); active_insts_in_pipeline--; } - if(!m_config->fast_execution_mode || active_insts_in_pipeline){ + if(active_insts_in_pipeline){ for( unsigned stage=0; (stage+1)<m_pipeline_depth; stage++ ) move_warp(m_pipeline_reg[stage], m_pipeline_reg[stage+1]); } @@ -2966,7 +2966,7 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const abort(); } - if(adpative_volta_cache_config && !k.volta_cache_config_set) { + if(adaptive_volta_cache_config && !k.volta_cache_config_set) { //For Volta, we assign the remaining shared memory to L1 cache //For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x unsigned total_shmed = kernel_info->smem * result; @@ -3000,7 +3000,6 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const void shader_core_config::set_pipeline_latency() { - if(fast_execution_mode) { //calculate the max latency based on the input unsigned int_latency[5]; @@ -3038,19 +3037,12 @@ void shader_core_config::set_pipeline_latency() { max_int_latency = int_latency[1]; max_dp_latency = dp_latency[1]; max_tensor_core_latency = tensor_latency; - } else { - max_sfu_latency = 512; - max_sp_latency = 32; - max_int_latency = 32; - max_dp_latency = 512; - max_tensor_core_latency = 64; - } } void shader_core_ctx::cycle() { - if(m_config->fast_execution_mode && !isactive() && get_not_completed() == 0) + if(!isactive() && get_not_completed() == 0) return; m_stats->shader_cycles[m_sid]++; |