0.9756 correlation. Set L1T line size to 128 bytes... problem was

stalling to send four requests per warp into L1T tag lookup.

If L1T is really 32B blocks (as per Henry's paper), this suggests 
banking of L1T needs to be modeled. 

Other changes:
1. bug fix in memory access generation for texture/const cache access
2. adding back memory latency measurement for visualizer

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]

1 files changed, 3 insertions, 1 deletions

diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 52a7e35..e85c210 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1166,7 +1166,8 @@ public:
                        unsigned cluster_id, 
                        const struct shader_core_config *config, 
                        const struct memory_config *mem_config,
-                       shader_core_stats *stats );
+                       shader_core_stats *stats,
+                       memory_stats_t *mstats );
 
     void core_cycle();
     void icnt_cycle();
@@ -1190,6 +1191,7 @@ private:
     gpgpu_sim *m_gpu;
     const shader_core_config *m_config;
     shader_core_stats *m_stats;
+    memory_stats_t *m_memory_stats;
     shader_core_ctx **m_core;
 
     unsigned m_cta_issue_next_core;