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authorMahmoud <[email protected]>2017-09-13 16:03:39 -0400
committerMahmoud <[email protected]>2017-09-13 16:03:39 -0400
commit355de7f8d033a4b5082cb0816650d880f05d81c8 (patch)
tree8a4c64e935caf189f2511cf9a20778e11a149ddf /src/gpgpu-sim/shader.h
parentbd45b8f49f35827dfaa7b5273dda85f0c442fe13 (diff)
Adding sperate dp_unit
Diffstat (limited to 'src/gpgpu-sim/shader.h')
-rw-r--r--src/gpgpu-sim/shader.h41
1 files changed, 36 insertions, 5 deletions
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 2fed420..544d8d8 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -326,12 +326,13 @@ public:
Scoreboard* scoreboard, simt_stack** simt,
std::vector<shd_warp_t>* warp,
register_set* sp_out,
+ register_set* dp_out,
register_set* sfu_out,
register_set* mem_out,
int id)
: m_supervised_warps(), m_stats(stats), m_shader(shader),
m_scoreboard(scoreboard), m_simt_stack(simt), /*m_pipeline_reg(pipe_regs),*/ m_warp(warp),
- m_sp_out(sp_out),m_sfu_out(sfu_out),m_mem_out(mem_out), m_id(id){}
+ m_sp_out(sp_out),m_dp_out(dp_out),m_sfu_out(sfu_out),m_mem_out(mem_out), m_id(id){}
virtual ~scheduler_unit(){}
virtual void add_supervised_warp_id(int i) {
m_supervised_warps.push_back(&warp(i));
@@ -403,6 +404,7 @@ protected:
//warp_inst_t** m_pipeline_reg;
std::vector<shd_warp_t>* m_warp;
register_set* m_sp_out;
+ register_set* m_dp_out;
register_set* m_sfu_out;
register_set* m_mem_out;
@@ -415,10 +417,11 @@ public:
Scoreboard* scoreboard, simt_stack** simt,
std::vector<shd_warp_t>* warp,
register_set* sp_out,
+ register_set* dp_out,
register_set* sfu_out,
register_set* mem_out,
int id )
- : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, mem_out, id ){}
+ : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, mem_out, id ){}
virtual ~lrr_scheduler () {}
virtual void order_warps ();
virtual void done_adding_supervised_warps() {
@@ -432,10 +435,11 @@ public:
Scoreboard* scoreboard, simt_stack** simt,
std::vector<shd_warp_t>* warp,
register_set* sp_out,
+ register_set* dp_out,
register_set* sfu_out,
register_set* mem_out,
int id )
- : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, mem_out, id ){}
+ : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, mem_out, id ){}
virtual ~gto_scheduler () {}
virtual void order_warps ();
virtual void done_adding_supervised_warps() {
@@ -450,10 +454,11 @@ public:
Scoreboard* scoreboard, simt_stack** simt,
std::vector<shd_warp_t>* warp,
register_set* sp_out,
+ register_set* dp_out,
register_set* sfu_out,
register_set* mem_out,
int id )
- : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, mem_out, id ){}
+ : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, mem_out, id ){}
virtual ~oldest_scheduler () {}
virtual void order_warps ();
virtual void done_adding_supervised_warps() {
@@ -468,11 +473,12 @@ public:
Scoreboard* scoreboard, simt_stack** simt,
std::vector<shd_warp_t>* warp,
register_set* sp_out,
+ register_set* dp_out,
register_set* sfu_out,
register_set* mem_out,
int id,
char* config_str )
- : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, mem_out, id ),
+ : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, mem_out, id ),
m_pending_warps()
{
unsigned inner_level_readin;
@@ -518,6 +524,7 @@ public:
Scoreboard* scoreboard, simt_stack** simt,
std::vector<shd_warp_t>* warp,
register_set* sp_out,
+ register_set* dp_out,
register_set* sfu_out,
register_set* mem_out,
int id,
@@ -1088,6 +1095,22 @@ public:
virtual void issue( register_set& source_reg );
};
+class dp_unit : public pipelined_simd_unit
+{
+public:
+ dp_unit( register_set* result_port, const shader_core_config *config, shader_core_ctx *core );
+ virtual bool can_issue( const warp_inst_t &inst ) const
+ {
+ switch(inst.op) {
+ case DP_OP: break;
+ default: return false;
+ }
+ return pipelined_simd_unit::can_issue(inst);
+ }
+ virtual void active_lanes_in_pipeline();
+ virtual void issue( register_set& source_reg );
+};
+
class sp_unit : public pipelined_simd_unit
{
public:
@@ -1226,9 +1249,11 @@ protected:
enum pipeline_stage_name_t {
ID_OC_SP=0,
+ ID_OC_DP,
ID_OC_SFU,
ID_OC_MEM,
OC_EX_SP,
+ OC_EX_DP,
OC_EX_SFU,
OC_EX_MEM,
EX_WB,
@@ -1237,9 +1262,11 @@ enum pipeline_stage_name_t {
const char* const pipeline_stage_name_decode[] = {
"ID_OC_SP",
+ "ID_OC_DP",
"ID_OC_SFU",
"ID_OC_MEM",
"OC_EX_SP",
+ "OC_EX_DP",
"OC_EX_SFU",
"OC_EX_MEM",
"EX_WB",
@@ -1328,21 +1355,25 @@ struct shader_core_config : public core_config
//op collector
int gpgpu_operand_collector_num_units_sp;
+ int gpgpu_operand_collector_num_units_dp;
int gpgpu_operand_collector_num_units_sfu;
int gpgpu_operand_collector_num_units_mem;
int gpgpu_operand_collector_num_units_gen;
unsigned int gpgpu_operand_collector_num_in_ports_sp;
+ unsigned int gpgpu_operand_collector_num_in_ports_dp;
unsigned int gpgpu_operand_collector_num_in_ports_sfu;
unsigned int gpgpu_operand_collector_num_in_ports_mem;
unsigned int gpgpu_operand_collector_num_in_ports_gen;
unsigned int gpgpu_operand_collector_num_out_ports_sp;
+ unsigned int gpgpu_operand_collector_num_out_ports_dp;
unsigned int gpgpu_operand_collector_num_out_ports_sfu;
unsigned int gpgpu_operand_collector_num_out_ports_mem;
unsigned int gpgpu_operand_collector_num_out_ports_gen;
int gpgpu_num_sp_units;
+ int gpgpu_num_dp_units;
int gpgpu_num_sfu_units;
int gpgpu_num_mem_units;