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authorDeval Shah <[email protected]>2018-11-09 21:14:55 -0800
committerDeval Shah <[email protected]>2018-11-09 21:14:55 -0800
commit36496d4ab2ff1088979e0f3137c54592652c37da (patch)
treeca449a4dc68abd5355764ae1bc50ca6ea5888fec /src/gpgpu-sim/shader.h
parent0265d747b06c18d0a1ee00fb1641032201425c97 (diff)
parent0e8d4f190940681601bdf7f95a5686baa0b6463b (diff)
resolving merge conflict
Diffstat (limited to 'src/gpgpu-sim/shader.h')
-rw-r--r--src/gpgpu-sim/shader.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 3542120..6e06322 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -565,7 +565,7 @@ public:
void init( unsigned num_banks, shader_core_ctx *shader );
// modifiers
- bool writeback( const warp_inst_t &warp ); // might cause stall
+ bool writeback( warp_inst_t &warp );
void step()
{
@@ -1392,7 +1392,8 @@ struct shader_core_config : public core_config
unsigned max_cta_per_core; //Limit on number of concurrent CTAs in shader core
unsigned max_barriers_per_cta;
char * gpgpu_scheduler_string;
-
+ unsigned gpgpu_shmem_per_block;
+ unsigned gpgpu_registers_per_block;
char* pipeline_widths_string;
int pipe_widths[N_PIPELINE_STAGES];