impl xor lane shuffling; add delay option for operand reads

1 files changed, 57 insertions, 4 deletions

diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index d8103ac..3d1aea9 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -751,6 +751,7 @@ class opndcoll_rfu_t {  // operand collector based register file unit
 
   void step() {
     dispatch_ready_cu();
+    drain_pending_operands();
     allocate_reads();
     for (unsigned p = 0; p < m_in_ports.size(); p++) allocate_cu(p);
     process_banks();
@@ -771,13 +772,22 @@ class opndcoll_rfu_t {  // operand collector based register file unit
  private:
   void process_banks() { m_arbiter.reset_alloction(); }
 
+  // types (forward-declared so member function signatures below can
+  // reference nested types defined later in this class body)
+  class op_t;
+  class collector_unit_t;
+
   void dispatch_ready_cu();
   void allocate_cu(unsigned port);
   void allocate_reads();
-
-  // types
-
-  class collector_unit_t;
+  // Deliver one allocated operand to its collector unit and bump the
+  // regfile-read stat. Shared by allocate_reads (latency=0 fast path)
+  // and drain_pending_operands (latency>0).
+  void deliver_operand(op_t &op);
+  // Drain any pending-operand queue entries whose cycle_ready has
+  // elapsed; called from step() between dispatch_ready_cu and
+  // allocate_reads so delivered operands dispatch on the *next* cycle.
+  void drain_pending_operands();
 
   class op_t {
    public:
@@ -1183,6 +1193,15 @@ class opndcoll_rfu_t {  // operand collector based register file unit
   // port_to_du_t                     m_dispatch_units;
   // std::map<warp_inst_t**,std::list<collector_unit_t*> > m_free_cu;
   shader_core_ctx *m_shader;
+
+  // Delay queue for modeling operand-collector read pipelining when
+  // `-gpgpu_opndcoll_read_latency > 0`. allocate_reads() pushes here;
+  // drain_pending_operands() pops at the top of step().
+  struct pending_operand_t {
+    op_t op;
+    unsigned long long cycle_ready;
+  };
+  std::deque<pending_operand_t> m_pending_operands;
 };
 
 class barrier_set_t {
@@ -1716,6 +1735,37 @@ class shader_core_config : public core_config {
       simd_set_width = warp_size;
     }
 
+    // --- Compaction-mode back-compat shim (Change 1) ---
+    // Old flag -gpgpu_enable_compaction maps to mode=2 (full).
+    // New flag -gpgpu_compaction_mode=2 re-asserts the old bool so
+    // the three existing call sites that still read the old flag
+    // continue to work unchanged. Change 2 will migrate the call
+    // sites to read gpgpu_compaction_mode directly.
+    if (gpgpu_compaction_mode > 2) {
+      fprintf(stderr,
+              "GPGPU-Sim: invalid -gpgpu_compaction_mode %u; must be "
+              "0, 1, or 2\n",
+              gpgpu_compaction_mode);
+      abort();
+    }
+    if (gpgpu_co_issue_priority > 4) {
+      fprintf(stderr,
+              "GPGPU-Sim: invalid -gpgpu_co_issue_priority %u; must be "
+              "in [0,4]\n",
+              gpgpu_co_issue_priority);
+      abort();
+    }
+    if (gpgpu_enable_compaction && gpgpu_compaction_mode == 0) {
+      gpgpu_compaction_mode = 2;
+    }
+    if (gpgpu_compaction_mode == 2) {
+      gpgpu_enable_compaction = true;
+    }
+    // Mode 1 (xor-static) has no existing-call-site equivalent yet;
+    // Change 2 wires it up. Until then, selecting mode=1 produces
+    // identity SIMD-set layout (compute_simd_sets) because
+    // gpgpu_enable_compaction is left as whatever the user set.
+
     set_pipeline_latency();
 
     m_L1I_config.init(m_L1I_config.m_config_string, FuncCachePreferNone);
@@ -1863,6 +1913,9 @@ class shader_core_config : public core_config {
   unsigned gpgpu_num_simd_sets;
   unsigned simd_set_width;  // derived: warp_size / num_simd_sets
   bool gpgpu_enable_compaction;
+  unsigned gpgpu_compaction_mode;       // 0=none, 1=xor-static, 2=full
+  unsigned gpgpu_opndcoll_read_latency; // extra cycles to collector
+  unsigned gpgpu_co_issue_priority;     // 0=greedy..4=same-PC
 
   unsigned n_simt_cores_per_cluster;
   unsigned n_simt_clusters;