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authorTayler Hetherington <[email protected]>2012-09-19 14:51:45 -0800
committerAndrew Boktor <[email protected]>2014-08-14 13:49:20 -0700
commitb09eeed6aa36239f661d6452e996e3e5f8ef5984 (patch)
tree1d71f118193e7eb8b8de79d3f08a934067e5a143 /src/gpgpu-sim/shader.h
parentb19fd89f07b3221ea73f6c2442880c2e5c1e68a5 (diff)
Revision #2 of modifying the cache hierarchy.
Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations. Added WRITE_EVICT cache write policy. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109]
Diffstat (limited to 'src/gpgpu-sim/shader.h')
-rw-r--r--src/gpgpu-sim/shader.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 078633d..262a3be 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -922,7 +922,7 @@ private:
tex_cache *m_L1T; // texture cache
read_only_cache *m_L1C; // constant cache
- data_cache *m_L1D; // data cache
+ l1_cache *m_L1D; // data cache
std::map<unsigned/*warp_id*/, std::map<unsigned/*regnum*/,unsigned/*count*/> > m_pending_writes;
std::list<mem_fetch*> m_response_fifo;
opndcoll_rfu_t *m_operand_collector;