- Adding support for cudaFuncSetCacheConfig API, that allows changing the

      L1 Cache and Shared Memory configurations across kernels. The support
      enable the user to specify two more configurations (Preferred L1) or
      (Preferred Shared Memory) besides the default config. If the
      cudaFuncSetCacheConfig API is used to set the cache configuration
      of a specific kernel to either of these configuration (cudaFuncCachePreferShared,
      cudaFuncCachePreferL1), the simulator will change the cache configuration
      at kernel launch accordingly, if there is no alternative configurations
      provided to the simulator it will use the default configurations with a
      warning message display

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15816]

1 files changed, 8 insertions, 8 deletions

diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index ba63634..4f5342f 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1208,10 +1208,10 @@ struct shader_core_config : public core_config
         assert( !(n_thread_per_shader % warp_size) );
         max_sfu_latency = 512;
         max_sp_latency = 32;
-        m_L1I_config.init();
-        m_L1T_config.init();
-        m_L1C_config.init();
-        m_L1D_config.init();
+        m_L1I_config.init(m_L1I_config.m_config_string);
+        m_L1T_config.init(m_L1T_config.m_config_string);
+        m_L1C_config.init(m_L1C_config.m_config_string);
+        m_L1D_config.init(m_L1D_config.m_config_string);
         gpgpu_cache_texl1_linesize = m_L1T_config.get_line_sz();
         gpgpu_cache_constl1_linesize = m_L1C_config.get_line_sz();
         m_valid = true;
@@ -1239,10 +1239,10 @@ struct shader_core_config : public core_config
     char* pipeline_widths_string;
     int pipe_widths[N_PIPELINE_STAGES];
 
-    cache_config m_L1I_config;
-    cache_config m_L1T_config;
-    cache_config m_L1C_config;
-    cache_config m_L1D_config;
+    mutable cache_config m_L1I_config;
+    mutable cache_config m_L1T_config;
+    mutable cache_config m_L1C_config;
+    mutable cache_config m_L1D_config;
 
     bool gpgpu_dwf_reg_bankconflict;