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authorMahmoud <[email protected]>2018-09-07 22:01:31 -0400
committerMahmoud <[email protected]>2018-09-07 22:01:31 -0400
commitf852a7108e691045dd3910065836a817babcde8c (patch)
tree16a83744048f5c2bd43dff818187786372047f00 /src/gpgpu-sim/shader.h
parentb013499f5f490086c7a7c5c28b04346e79ab2635 (diff)
adding streamin cache + fixing TEX cache + adding l1 latency and smem latency
Diffstat (limited to 'src/gpgpu-sim/shader.h')
-rw-r--r--src/gpgpu-sim/shader.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index cc441b3..e07096e 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1220,6 +1220,7 @@ protected:
mem_fetch *mf,
enum cache_request_status status );
mem_stage_stall_type process_memory_access_queue( cache_t *cache, warp_inst_t &inst );
+ mem_stage_stall_type process_memory_access_queue_l1cache( l1_cache *cache, warp_inst_t &inst );
const memory_config *m_memory_config;
class mem_fetch_interface *m_icnt;
@@ -1248,6 +1249,9 @@ protected:
// for debugging
unsigned long long m_last_inst_gpu_sim_cycle;
unsigned long long m_last_inst_gpu_tot_sim_cycle;
+
+ std::deque<mem_fetch* > l1_latency_queue;
+ void L1_latency_queue_cycle();
};
enum pipeline_stage_name_t {
@@ -1399,6 +1403,8 @@ struct shader_core_config : public core_config
int simt_core_sim_order;
+ unsigned smem_latency;
+
unsigned mem2device(unsigned memid) const { return memid + n_simt_clusters; }
//Jin: concurrent kernel on sm