critical fix - add option to have masks for SB entries

1 files changed, 36 insertions, 1 deletions

diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 51ed214..ebcfc8d 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1659,13 +1659,27 @@ class ldst_unit : public pipelined_simd_unit {
   mem_stage_stall_type process_memory_access_queue_l1cache(l1_cache *cache,
                                                            warp_inst_t &inst);
 
+  // Mode 1 helper: decrement m_pending_writes_mask[wid][reg][mask] and, if
+  // it hits zero, release the (reg, mask) entry in the mask-aware
+  // scoreboard. No-op in mode 0. Inline here so the compiler can elide the
+  // mode-0 path entirely.
+  void dec_mask_pw_and_maybe_release(unsigned wid, unsigned reg,
+                                     const active_mask_t &mask);
+
   // MEM co-issue: resolve which source warp + instruction an access/mem_fetch
   // belongs to (for routing pending_writes / scoreboard release back to the
   // originating warp under composites). Returns {src_wid, src_out_inst}.
   // For non-composite or primary-source accesses, returns {primary_wid, &inst}.
   // split_id differentiates intra-warp co-issued sets (same wid as primary)
   // from the primary set itself; use (unsigned)-1 when not applicable.
-  struct mem_src_t { unsigned wid; const inst_t *out_inst; };
+  struct mem_src_t {
+    unsigned wid;
+    const inst_t *out_inst;
+    // Mode 1: source_inst's full issue mask, looked up from the
+    // matching simd_set's source_mask. Empty for primary access (which
+    // uses pipe_reg's own get_active_mask() at release time).
+    active_mask_t source_mask;
+  };
   mem_src_t resolve_source(const warp_inst_t &inst,
                             unsigned access_src_wid,
                             unsigned access_src_split_id) const;
@@ -1721,6 +1735,19 @@ class ldst_unit : public pipelined_simd_unit {
            std::map<unsigned /*split_id*/,
                     std::map<unsigned /*reg*/, unsigned /*count*/>>>
       m_pending_writes_secondary;
+  // Mode 1 (mask-aware scoreboard) pending-writes counter, keyed by
+  // (wid, reg, mask). Mode 0's m_pending_writes aggregates across all
+  // in-flight insts to the same (wid, reg), which is fine for mode 0's
+  // single-entry-per-(wid,reg) scoreboard but causes leaks under mode 1's
+  // per-mask scoreboard: when the aggregate hits zero only the
+  // last-retiring access's mask gets a scoreboard release; other masks
+  // leak. This per-mask counter fires the mask-aware release at the
+  // correct time for each inst. Updated only when mode==1.
+  std::map<unsigned /*wid*/,
+           std::map<unsigned /*reg*/,
+                    std::map<unsigned long /*mask.to_ulong()*/,
+                             unsigned /*count*/>>>
+      m_pending_writes_mask;
   unsigned m_writeback_arb;  // round-robin arbiter for writeback contention
                              // between L1T, L1C, shared
   unsigned m_num_writeback_clients;
@@ -1851,6 +1878,13 @@ class shader_core_config : public core_config {
               gpgpu_co_issue_priority);
       abort();
     }
+    if (gpgpu_scoreboard_mode > 2) {
+      fprintf(stderr,
+              "GPGPU-Sim: invalid -gpgpu_scoreboard_mode %u; must be "
+              "0 (legacy), 1 (mask-aware), or 2 (slot-pinned)\n",
+              gpgpu_scoreboard_mode);
+      abort();
+    }
     if (gpgpu_enable_compaction && gpgpu_compaction_mode == 0) {
       gpgpu_compaction_mode = 2;
     }
@@ -2014,6 +2048,7 @@ class shader_core_config : public core_config {
   unsigned gpgpu_co_issue_priority;     // 0=greedy..4=same-PC
   bool gpgpu_simd_partitioning_debug;   // verbose SIMD_SETS printf gate
   bool gpgpu_mem_coissue;               // enable MEM/LDST co-issue path
+  unsigned gpgpu_scoreboard_mode;       // 0=legacy, 1=mask-aware, 2=slot-pinned
 
   unsigned n_simt_cores_per_cluster;
   unsigned n_simt_clusters;