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authorTor Aamodt <[email protected]>2010-10-16 17:30:52 -0800
committerTor Aamodt <[email protected]>2010-10-16 17:30:52 -0800
commitb577cbcdf229a2c02d1bf8584c6e82be7a14cb33 (patch)
tree373ea8ec8ea8d7d9a7a1df0eaa17f15652df1306 /src/gpgpu-sim/stats.h
parent2072e7ff2037c19a0c346e60469949c9437569bf (diff)
1. creating cache_config object to encapsulate cache configuration information
(and parse it before creating the simulator objects). 2. creating core_config to hold only features of a shader_core that are high level enough either (a) the functional simulator needs to know about them, or (b) they affect memory *access* generation. 3. in config files only (so far) separate out notion of write-{through,back}, from notion of when a line is allocated... will use this to distinguish different types of caches. passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7870]
Diffstat (limited to 'src/gpgpu-sim/stats.h')
-rw-r--r--src/gpgpu-sim/stats.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gpgpu-sim/stats.h b/src/gpgpu-sim/stats.h
index 20acfa1..8115eae 100644
--- a/src/gpgpu-sim/stats.h
+++ b/src/gpgpu-sim/stats.h
@@ -90,7 +90,7 @@ enum mem_stage_stall_type {
N_MEM_STAGE_STALL_TYPE
};
-struct shader_core_stats
+struct shader_core_stats
{
unsigned int gpgpu_n_load_insn;
unsigned int gpgpu_n_store_insn;