1. rewriting memory access generation code (from scratch), why not...

passing CUDA 3.1 and ptxplus correlation, but correlation still bad (0.62)... 

after debugging 1 to get it working with ptxplus, problem is very clear:
shared and constant cache accesses not occuring for operations that combine these with ALU operations.

TODO: 
have a "read-operands" stage, which somehow combines operand collector 
register reading with shared and const memory accesses...

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7895]

1 files changed, 2 insertions, 2 deletions

diff --git a/src/gpgpu-sim/visualizer.cc b/src/gpgpu-sim/visualizer.cc
index 51348d5..730e0c9 100644
--- a/src/gpgpu-sim/visualizer.cc
+++ b/src/gpgpu-sim/visualizer.cc
@@ -483,7 +483,7 @@ void time_vector_print_interval2gzfile(gzFile outfile) {
 void time_vector_update(unsigned int uid,int slot ,long int cycle,int type) {
    if ( (type == RD_REQ) || (type == REPLY_DATA) ) {
       g_my_time_vector->update_ld( uid, slot,cycle);
-   } else if ( type == WT_REQ ) {
+   } else if ( type == WR_REQ ) {
       g_my_time_vector->update_st( uid, slot,cycle);
    } else {
       abort(); 
@@ -494,7 +494,7 @@ void check_time_vector_update(unsigned int uid,int slot ,long int latency,int ty
 {
    if ( (type == RD_REQ) || (type == REPLY_DATA) ) {
       g_my_time_vector->check_ld_update( uid, slot, latency );
-   } else if ( type == WT_REQ ) {
+   } else if ( type == WR_REQ ) {
       g_my_time_vector->check_st_update( uid, slot, latency );
    } else {
       abort();