Merge pull request #80 from AamirRaihan/dev

Merging Tensor Cores code

4 files changed, 202 insertions, 60 deletions

diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index d02e8e1..a8be4d2 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -356,6 +356,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_operand_collector_num_units_sfu", OPT_INT32, &gpgpu_operand_collector_num_units_sfu,
                 "number of collector units (default = 4)", 
                 "4");
+    option_parser_register(opp, "-gpgpu_operand_collector_num_units_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_units_tensor_core,
+                "number of collector units (default = 4)", 
+                "4");
     option_parser_register(opp, "-gpgpu_operand_collector_num_units_mem", OPT_INT32, &gpgpu_operand_collector_num_units_mem,
                 "number of collector units (default = 2)", 
                 "2");
@@ -371,6 +374,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_sfu", OPT_INT32, &gpgpu_operand_collector_num_in_ports_sfu,
                            "number of collector unit in ports (default = 1)", 
                            "1");
+    option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_in_ports_tensor_core,
+                           "number of collector unit in ports (default = 1)", 
+                           "1");
     option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_mem", OPT_INT32, &gpgpu_operand_collector_num_in_ports_mem,
                            "number of collector unit in ports (default = 1)", 
                            "1");
@@ -386,6 +392,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_sfu", OPT_INT32, &gpgpu_operand_collector_num_out_ports_sfu,
                            "number of collector unit in ports (default = 1)", 
                            "1");
+    option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_out_ports_tensor_core,
+                           "number of collector unit in ports (default = 1)", 
+                           "1");
     option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_mem", OPT_INT32, &gpgpu_operand_collector_num_out_ports_mem,
                            "number of collector unit in ports (default = 1)", 
                            "1");
@@ -409,8 +418,11 @@ void shader_core_config::reg_options(class OptionParser * opp)
                             "1");
     option_parser_register(opp, "-gpgpu_pipeline_widths", OPT_CSTR, &pipeline_widths_string,
                             "Pipeline widths "
-                            "ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB",
-                            "1,1,1,1,1,1,1,1,1" );
+                            "ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE",
+                            "1,1,1,1,1,1,1,1,1,1,1" );
+    option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_INT32, &gpgpu_tensor_core_avail,
+                            "Tensor Core Available (default=0)",
+                            "0");
     option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32, &gpgpu_num_sp_units,
                             "Number of SP units (default=1)",
                             "1");
@@ -420,6 +432,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_INT32, &gpgpu_num_sfu_units,
                             "Number of SF units (default=1)",
                             "1");
+    option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32, &gpgpu_num_tensor_core_units,
+                            "Number of tensor_core units (default=1)",
+                            "1");
     option_parser_register(opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units,
                             "Number if ldst units (default=1) WARNING: not hooked up to anything",
                              "1");
@@ -1178,6 +1193,9 @@ void shader_core_ctx::mem_instruction_stats(const warp_inst_t &inst)
     case shared_space:
         m_stats->gpgpu_n_shmem_insn += active_count; 
         break;
+    case sstarr_space:
+    	m_stats->gpgpu_n_sstarr_insn += active_count;
+    	break;
     case const_space:
         m_stats->gpgpu_n_const_insn += active_count;
         break;
@@ -1553,7 +1571,8 @@ void gpgpu_sim::cycle()
       if( g_single_step && ((gpu_sim_cycle+gpu_tot_sim_cycle) >= g_single_step) ) {
           raise(SIGTRAP); // Debug breakpoint
       }
-      gpu_sim_cycle++;
+	 gpu_sim_cycle++;
+	
       if( g_interactive_debugger_enabled ) 
          gpgpu_debug();
 
@@ -1643,7 +1662,7 @@ void gpgpu_sim::cycle()
          }
       }
 
-      if (!(gpu_sim_cycle % 20000)) {
+      if (!(gpu_sim_cycle % 50000)) {
          // deadlock detection 
          if (m_config.gpu_deadlock_detect && gpu_sim_insn == last_gpu_sim_insn) {
             gpu_deadlock = true;
diff --git a/src/gpgpu-sim/scoreboard.cc b/src/gpgpu-sim/scoreboard.cc
index f412054..ebec891 100644
--- a/src/gpgpu-sim/scoreboard.cc
+++ b/src/gpgpu-sim/scoreboard.cc
@@ -82,7 +82,7 @@ const bool Scoreboard::islongop (unsigned warp_id,unsigned regnum) {
 
 void Scoreboard::reserveRegisters(const class warp_inst_t* inst) 
 {
-    for( unsigned r=0; r < 4; r++) {
+    for( unsigned r=0; r < MAX_OUTPUT_VALUES; r++) {
         if(inst->out[r] > 0) {
             reserveRegister(inst->warp_id(), inst->out[r]);
             SHADER_DPRINTF( SCOREBOARD,
@@ -100,7 +100,7 @@ void Scoreboard::reserveRegisters(const class warp_inst_t* inst)
                 inst->space.get_type() == param_space_local ||
                 inst->space.get_type() == param_space_unclassified ||
     			inst->space.get_type() == tex_space)){
-    	for ( unsigned r=0; r<4; r++) {
+    	for ( unsigned r=0; r<MAX_OUTPUT_VALUES; r++) {
     		if(inst->out[r] > 0) {
                 SHADER_DPRINTF( SCOREBOARD,
                                 "New longopreg marked - warp:%d, reg: %d\n",
@@ -115,7 +115,7 @@ void Scoreboard::reserveRegisters(const class warp_inst_t* inst)
 // Release registers for an instruction
 void Scoreboard::releaseRegisters(const class warp_inst_t *inst) 
 {
-    for( unsigned r=0; r < 4; r++) {
+    for( unsigned r=0; r < MAX_OUTPUT_VALUES; r++) {
         if(inst->out[r] > 0) {
             SHADER_DPRINTF( SCOREBOARD,
                             "Register Released - warp:%d, reg: %d\n",
@@ -138,15 +138,13 @@ bool Scoreboard::checkCollision( unsigned wid, const class inst_t *inst ) const
 	// Get list of all input and output registers
 	std::set<int> inst_regs;
 
-	if(inst->out[0] > 0) inst_regs.insert(inst->out[0]);
-	if(inst->out[1] > 0) inst_regs.insert(inst->out[1]);
-	if(inst->out[2] > 0) inst_regs.insert(inst->out[2]);
-	if(inst->out[3] > 0) inst_regs.insert(inst->out[3]);
-	if(inst->in[0] > 0) inst_regs.insert(inst->in[0]);
-	if(inst->in[1] > 0) inst_regs.insert(inst->in[1]);
-	if(inst->in[2] > 0) inst_regs.insert(inst->in[2]);
-	if(inst->in[3] > 0) inst_regs.insert(inst->in[3]);
-	if(inst->pred > 0) inst_regs.insert(inst->pred);
+	for(int iii=0;iii<inst->outcount;iii++)
+		inst_regs.insert(inst->out[iii]);
+
+	for(int jjj=0;jjj<inst->incount;jjj++)
+		inst_regs.insert(inst->in[jjj]);
+
+        if(inst->pred > 0) inst_regs.insert(inst->pred);
 	if(inst->ar1 > 0) inst_regs.insert(inst->ar1);
 	if(inst->ar2 > 0) inst_regs.insert(inst->ar2);
 
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 8a84970..cd2ed26 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -152,6 +152,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                        &m_pipeline_reg[ID_OC_SP],
 									   &m_pipeline_reg[ID_OC_DP],
                                        &m_pipeline_reg[ID_OC_SFU],
+                                       &m_pipeline_reg[ID_OC_TENSOR_CORE],
                                        &m_pipeline_reg[ID_OC_MEM],
                                        i
                                      )
@@ -167,6 +168,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                                     &m_pipeline_reg[ID_OC_SP],
 													&m_pipeline_reg[ID_OC_DP],
                                                     &m_pipeline_reg[ID_OC_SFU],
+                                                    &m_pipeline_reg[ID_OC_TENSOR_CORE],
                                                     &m_pipeline_reg[ID_OC_MEM],
                                                     i,
                                                     config->gpgpu_scheduler_string
@@ -183,6 +185,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                        &m_pipeline_reg[ID_OC_SP],
 									   &m_pipeline_reg[ID_OC_DP],
                                        &m_pipeline_reg[ID_OC_SFU],
+                                       &m_pipeline_reg[ID_OC_TENSOR_CORE],
                                        &m_pipeline_reg[ID_OC_MEM],
                                        i
                                      )
@@ -198,6 +201,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
 					  &m_pipeline_reg[ID_OC_SP],
 					  &m_pipeline_reg[ID_OC_DP],
 					  &m_pipeline_reg[ID_OC_SFU],
+                                       	  &m_pipeline_reg[ID_OC_TENSOR_CORE],
 					  &m_pipeline_reg[ID_OC_MEM],
 					  i
 					 )
@@ -213,6 +217,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                        &m_pipeline_reg[ID_OC_SP],
 									   &m_pipeline_reg[ID_OC_DP],
                                        &m_pipeline_reg[ID_OC_SFU],
+                                       &m_pipeline_reg[ID_OC_TENSOR_CORE],
                                        &m_pipeline_reg[ID_OC_MEM],
                                        i,
                                        config->gpgpu_scheduler_string
@@ -233,10 +238,11 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
     }
     
     //op collector configuration
-    enum { SP_CUS, DP_CUS, SFU_CUS, MEM_CUS, GEN_CUS };
+    enum { SP_CUS, DP_CUS, SFU_CUS, TENSOR_CORE_CUS, MEM_CUS,  GEN_CUS };
     m_operand_collector.add_cu_set(SP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_sp);
     m_operand_collector.add_cu_set(DP_CUS, m_config->gpgpu_operand_collector_num_units_dp, m_config->gpgpu_operand_collector_num_out_ports_dp);
     m_operand_collector.add_cu_set(SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu);
+    m_operand_collector.add_cu_set(TENSOR_CORE_CUS, config->gpgpu_operand_collector_num_units_tensor_core, config->gpgpu_operand_collector_num_out_ports_tensor_core);
     m_operand_collector.add_cu_set(MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem, m_config->gpgpu_operand_collector_num_out_ports_mem);
     m_operand_collector.add_cu_set(GEN_CUS, m_config->gpgpu_operand_collector_num_units_gen, m_config->gpgpu_operand_collector_num_out_ports_gen);
     
@@ -269,6 +275,15 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
         m_operand_collector.add_port(in_ports,out_ports,cu_sets);
         in_ports.clear(),out_ports.clear(),cu_sets.clear();
     }
+
+    for (unsigned i = 0; i < config->gpgpu_operand_collector_num_in_ports_tensor_core; i++) {
+        in_ports.push_back(&m_pipeline_reg[ID_OC_TENSOR_CORE]);
+        out_ports.push_back(&m_pipeline_reg[OC_EX_TENSOR_CORE]);
+        cu_sets.push_back((unsigned)TENSOR_CORE_CUS);
+        cu_sets.push_back((unsigned)GEN_CUS);
+        m_operand_collector.add_port(in_ports,out_ports,cu_sets);
+        in_ports.clear(),out_ports.clear(),cu_sets.clear();
+    }
     
     for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_mem; i++) {
         in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]);
@@ -283,9 +298,11 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
     for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_gen; i++) {
         in_ports.push_back(&m_pipeline_reg[ID_OC_SP]);
         in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]);
+        in_ports.push_back(&m_pipeline_reg[ID_OC_TENSOR_CORE]);
         in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]);
         out_ports.push_back(&m_pipeline_reg[OC_EX_SP]);
         out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]);
+        out_ports.push_back(&m_pipeline_reg[OC_EX_TENSOR_CORE]);
         out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]);
         cu_sets.push_back((unsigned)GEN_CUS);   
         m_operand_collector.add_port(in_ports,out_ports,cu_sets);
@@ -294,8 +311,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
     
     m_operand_collector.init( m_config->gpgpu_num_reg_banks, this );
     
-    // execute
-    m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_dp_units + m_config->gpgpu_num_sfu_units + 1; // sp_unit, sfu, ldst_unit
+    m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_dp_units + m_config->gpgpu_num_sfu_units + m_config->gpgpu_num_tensor_core_units + 1; // sp_unit, sfu, ldst_unit
     //m_dispatch_port = new enum pipeline_stage_name_t[ m_num_function_units ];
     //m_issue_port = new enum pipeline_stage_name_t[ m_num_function_units ];
     
@@ -318,12 +334,17 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
         m_dispatch_port.push_back(ID_OC_SFU);
         m_issue_port.push_back(OC_EX_SFU);
     }
-
+       
+    for (int k = 0; k < config->gpgpu_num_tensor_core_units; k++) {
+        m_fu.push_back(new tensor_core( &m_pipeline_reg[EX_WB], m_config, this ));
+        m_dispatch_port.push_back(ID_OC_TENSOR_CORE);
+        m_issue_port.push_back(OC_EX_TENSOR_CORE);
+    }
     m_ldst_unit = new ldst_unit( m_icnt, m_mem_fetch_allocator, this, &m_operand_collector, m_scoreboard, config, mem_config, stats, shader_id, tpc_id );
     m_fu.push_back(m_ldst_unit);
     m_dispatch_port.push_back(ID_OC_MEM);
     m_issue_port.push_back(OC_EX_MEM);
-    
+   
     assert(m_num_function_units == m_fu.size() and m_fu.size() == m_dispatch_port.size() and m_fu.size() == m_issue_port.size());
     
     //there are as many result buses as the width of the EX_WB stage
@@ -455,6 +476,7 @@ void shader_core_stats::print( FILE* fout ) const
    fprintf(fout, "gpgpu_n_load_insn  = %d\n", gpgpu_n_load_insn);
    fprintf(fout, "gpgpu_n_store_insn = %d\n", gpgpu_n_store_insn);
    fprintf(fout, "gpgpu_n_shmem_insn = %d\n", gpgpu_n_shmem_insn);
+   fprintf(fout, "gpgpu_n_sstarr_insn = %d\n", gpgpu_n_sstarr_insn);
    fprintf(fout, "gpgpu_n_tex_insn = %d\n", gpgpu_n_tex_insn);
    fprintf(fout, "gpgpu_n_const_mem_insn = %d\n", gpgpu_n_const_insn);
    fprintf(fout, "gpgpu_n_param_mem_insn = %d\n", gpgpu_n_param_insn);
@@ -758,7 +780,10 @@ void shader_core_ctx::func_exec_inst( warp_inst_t &inst )
 {
     execute_warp_inst_t(inst);
     if( inst.is_load() || inst.is_store() )
-        inst.generate_mem_accesses();
+    {
+	inst.generate_mem_accesses();
+        //inst.print_m_accessq();	
+    }	
 }
 
 void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* next_inst, const active_mask_t &active_mask, unsigned warp_id )
@@ -949,20 +974,21 @@ void scheduler_unit::cycle()
                         ready_inst = true;
                         const active_mask_t &active_mask = m_simt_stack[warp_id]->get_active_mask();
                         assert( warp(warp_id).inst_in_pipeline() );
-                        if ( (pI->op == LOAD_OP) || (pI->op == STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) {
-                        	if( m_mem_out->has_free() && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::MEM)) {
-                                m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id);
-                                issued++;
-                                issued_inst=true;
-                                warp_inst_issued = true;
-                                previous_issued_inst_exec_type = exec_unit_type_t::MEM;
-                            }
+                        if ( (pI->op == LOAD_OP) || (pI->op == STORE_OP) || (pI->op == MEMORY_BARRIER_OP)||(pI->op==TENSOR_CORE_LOAD_OP)||(pI->op==TENSOR_CORE_STORE_OP) ) {
+                        	if( m_mem_out->has_free() && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::MEM)) 			{
+                                	m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id);
+                                	issued++;
+                               	 	issued_inst=true;
+                                	warp_inst_issued = true;
+                                	previous_issued_inst_exec_type = exec_unit_type_t::MEM;
+                            	}
                         } else {
 
                             bool sp_pipe_avail = m_sp_out->has_free();
                             bool sfu_pipe_avail = m_sfu_out->has_free();
+                            bool tensor_core_pipe_avail = m_tensor_core_out->has_free();
                             bool dp_pipe_avail = m_dp_out->has_free();
-                            if( sp_pipe_avail && (pI->op != SFU_OP && pI->op != DP_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SP)) {
+                            if( sp_pipe_avail && (pI->op != TENSOR_CORE_OP) && (pI->op != SFU_OP && pI->op != DP_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SP)) {
                                 
                                 //Jin: special for CDP api
                                 if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) {
@@ -1005,12 +1031,21 @@ void scheduler_unit::cycle()
                                     warp_inst_issued = true;
                                     previous_issued_inst_exec_type = exec_unit_type_t::SFU;
                                 }
-                            }
-                        }
-                    } else {
+                            }                         
+                             else if ( (pI->op == TENSOR_CORE_OP) ) {
+                                if( tensor_core_pipe_avail ) {
+                                    m_shader->issue_warp(*m_tensor_core_out,pI,active_mask,warp_id);
+                                    issued++;
+                                    issued_inst=true;
+                                    warp_inst_issued = true;
+                                }
+			    }
+                         }//end of else
+                   } else {
+
                         SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails scoreboard\n",
                                        (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() );
-                    }
+                   }
                 }
             } else if( valid ) {
                // this case can happen after a return instruction in diverged warp
@@ -1144,7 +1179,7 @@ void two_level_active_scheduler::order_warps()
     for (   std::vector< shd_warp_t* >::iterator iter = m_next_cycle_prioritized_warps.begin();
             iter != m_next_cycle_prioritized_warps.end(); ) {
         bool waiting = (*iter)->waiting();
-        for (int i=0; i<4; i++){
+        for (int i=0; i<MAX_INPUT_VALUES; i++){
             const warp_inst_t* inst = (*iter)->ibuffer_next_inst();
             //Is the instruction waiting on a long operation?
             if ( inst && inst->in[i] > 0 && this->m_scoreboard->islongop((*iter)->get_warp_id(), inst->in[i])){
@@ -1190,10 +1225,11 @@ swl_scheduler::swl_scheduler ( shader_core_stats* stats, shader_core_ctx* shader
                                register_set* sp_out,
 							   register_set* dp_out,
                                register_set* sfu_out,
+                               register_set* tensor_core_out,
                                register_set* mem_out,
                                int id,
                                char* config_string )
-    : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, mem_out, id )
+    : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id )
 {
     unsigned m_prioritization_readin;
     int ret = sscanf( config_string,
@@ -1361,10 +1397,12 @@ void ldst_unit::get_L1T_sub_stats(struct cache_sub_stats &css) const{
 
 void shader_core_ctx::warp_inst_complete(const warp_inst_t &inst)
 {
-   #if 0
-      printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%#x @ time=%llu issued@%llu\n", 
-             inst.get_uid(), m_sid, inst.warp_id(), inst.pc, gpu_tot_sim_cycle + gpu_sim_cycle, inst.get_issue_cycle()); 
-   #endif
+
+  #if 0
+      printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%#x @ time=%llu issued@%llu\n",
+             inst.get_uid(), m_sid, inst.warp_id(), inst.pc, gpu_tot_sim_cycle + gpu_sim_cycle, inst.get_issue_cycle());
+  #endif
+
   if(inst.op_pipe==SP__OP)
 	  m_stats->m_num_sp_committed[m_sid]++;
   else if(inst.op_pipe==SFU__OP)
@@ -1467,7 +1505,7 @@ ldst_unit::process_cache_access( cache_t* cache,
         assert( !read_sent );
         inst.accessq_pop_back();
         if ( inst.is_load() ) {
-            for ( unsigned r=0; r < 4; r++)
+            for ( unsigned r=0; r < MAX_OUTPUT_VALUES; r++)
                 if (inst.out[r] > 0)
                     m_pending_writes[inst.warp_id()][inst.out[r]]--; 
         }
@@ -1561,7 +1599,7 @@ void ldst_unit::L1_latency_queue_cycle()
 			   assert( !read_sent );
 			   l1_latency_queue[0] = NULL;
 			   if ( mf_next->get_inst().is_load() ) {
-				   for ( unsigned r=0; r < 4; r++)
+				   for ( unsigned r=0; r < MAX_OUTPUT_VALUES; r++)
 					   if (mf_next->get_inst().out[r] > 0)
 					   {
 						   assert(m_pending_writes[mf_next->get_inst().warp_id()][mf_next->get_inst().out[r]]>0);
@@ -1661,11 +1699,11 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea
        if (m_core->get_config()->gmem_skip_L1D && (CACHE_L1 != inst.cache_op))
            bypassL1D = true; 
    }
-
    if( bypassL1D ) {
        // bypass L1 cache
        unsigned control_size = inst.is_store() ? WRITE_PACKET_SIZE : READ_PACKET_SIZE;
        unsigned size = access.get_size() + control_size;
+       //printf("Interconnect:Addr: %x, size=%d\n",access.get_addr(),size);
        if( m_icnt->full(size, inst.is_store() || inst.isatomic()) ) {
            stall_cond = ICNT_RC_FAIL;
        } else {
@@ -1674,7 +1712,7 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea
            inst.accessq_pop_back();
            //inst.clear_active( access.get_warp_mask() );
            if( inst.is_load() ) { 
-              for( unsigned r=0; r < 4; r++) 
+              for( unsigned r=0; r < MAX_OUTPUT_VALUES; r++) 
                   if(inst.out[r] > 0) 
                       assert( m_pending_writes[inst.warp_id()][inst.out[r]] > 0 );
            } else if( inst.is_store() ) 
@@ -1732,6 +1770,12 @@ sfu:: sfu(  register_set* result_port, const shader_core_config *config,shader_c
     m_name = "SFU"; 
 }
 
+tensor_core:: tensor_core(  register_set* result_port, const shader_core_config *config,shader_core_ctx *core  )
+    : pipelined_simd_unit(result_port,config,config->max_tensor_core_latency,core)
+{ 
+    m_name = "TENSOR_CORE"; 
+}
+
 void sfu::issue( register_set& source_reg )
 {
     warp_inst_t** ready_reg = source_reg.get_ready();
@@ -1742,6 +1786,17 @@ void sfu::issue( register_set& source_reg )
 	pipelined_simd_unit::issue(source_reg);
 }
 
+void tensor_core::issue( register_set& source_reg )
+{
+    warp_inst_t** ready_reg = source_reg.get_ready();
+	//m_core->incexecstat((*ready_reg));
+
+	(*ready_reg)->op_pipe= TENSOR_CORE__OP;
+	m_core->incsfu_stat(m_core->get_config()->warp_size,(*ready_reg)->latency);
+	pipelined_simd_unit::issue(source_reg);
+}
+
+
 void ldst_unit::active_lanes_in_pipeline(){
 	unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline();
 	assert(active_count<=m_core->get_config()->warp_size);
@@ -1770,6 +1825,15 @@ void sfu::active_lanes_in_pipeline(){
 	m_core->incfumemactivelanes_stat(active_count);
 }
 
+void tensor_core::active_lanes_in_pipeline(){
+	unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline();
+	assert(active_count<=m_core->get_config()->warp_size);
+	m_core->incsfuactivelanes_stat(active_count);
+	m_core->incfuactivelanes_stat(active_count);
+	m_core->incfumemactivelanes_stat(active_count);
+}
+
+
 sp_unit::sp_unit( register_set* result_port, const shader_core_config *config,shader_core_ctx *core)
     : pipelined_simd_unit(result_port,config,config->max_sp_latency,core)
 { 
@@ -1958,7 +2022,7 @@ void ldst_unit:: issue( register_set &reg_set )
    if (inst->is_load() and inst->space.get_type() != shared_space) {
       unsigned warp_id = inst->warp_id();
       unsigned n_accesses = inst->accessq_count();
-      for (unsigned r = 0; r < 4; r++) {
+      for (unsigned r = 0; r < MAX_OUTPUT_VALUES; r++) {
          unsigned reg_id = inst->out[r];
          if (reg_id > 0) {
             m_pending_writes[warp_id][reg_id] += n_accesses;
@@ -1980,7 +2044,7 @@ void ldst_unit::writeback()
     if( !m_next_wb.empty() ) {
         if( m_operand_collector->writeback(m_next_wb) ) {
             bool insn_completed = false; 
-            for( unsigned r=0; r < 4; r++ ) {
+            for( unsigned r=0; r < MAX_OUTPUT_VALUES; r++ ) {
                 if( m_next_wb.out[r] > 0 ) {
                     if( m_next_wb.space.get_type() != shared_space ) {
                         assert( m_pending_writes[m_next_wb.warp_id()][m_next_wb.out[r]] > 0 );
@@ -2082,7 +2146,7 @@ void ldst_unit::issue( register_set &reg_set )
    if (inst->is_load() and inst->space.get_type() != shared_space) {
       unsigned warp_id = inst->warp_id(); 
       unsigned n_accesses = inst->accessq_count(); 
-      for (unsigned r = 0; r < 4; r++) {
+      for (unsigned r = 0; r < MAX_OUTPUT_VALUES; r++) {
          unsigned reg_id = inst->out[r]; 
          if (reg_id > 0) {
             m_pending_writes[warp_id][reg_id] += n_accesses; 
@@ -2186,7 +2250,7 @@ void ldst_unit::cycle()
                //} 
 
                bool pending_requests=false;
-               for( unsigned r=0; r<4; r++ ) {
+               for( unsigned r=0; r<MAX_OUTPUT_VALUES; r++ ) {
                    unsigned reg_id = pipe_reg.out[r];
                    if( reg_id > 0 ) {
                        if( m_pending_writes[warp_id].find(reg_id) != m_pending_writes[warp_id].end() ) {
@@ -2494,7 +2558,7 @@ void shader_core_ctx::incexecstat(warp_inst_t *&inst)
 
 	switch(inst->sp_op){
 	case INT__OP:
-		incialu_stat(inst->active_count(),25);
+		incialu_stat(inst->active_count(),32);
 		break;
 	case INT_MUL_OP:
 		incimul_stat(inst->active_count(),7.2);
@@ -3664,6 +3728,7 @@ void simt_core_cluster::icnt_inject_request_packet(class mem_fetch *mf)
     case CONST_ACC_R: m_stats->gpgpu_n_mem_const++; break;
     case TEXTURE_ACC_R: m_stats->gpgpu_n_mem_texture++; break;
     case GLOBAL_ACC_R: m_stats->gpgpu_n_mem_read_global++; break;
+    //case GLOBAL_ACC_R: m_stats->gpgpu_n_mem_read_global++; printf("read_global%d\n",m_stats->gpgpu_n_mem_read_global); break;
     case GLOBAL_ACC_W: m_stats->gpgpu_n_mem_write_global++; break;
     case LOCAL_ACC_R: m_stats->gpgpu_n_mem_read_local++; break;
     case LOCAL_ACC_W: m_stats->gpgpu_n_mem_write_local++; break;
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 4a87126..3542120 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -328,11 +328,12 @@ public:
                    register_set* sp_out,
 				   register_set* dp_out,
                    register_set* sfu_out,
+                   register_set* tensor_core_out,
                    register_set* mem_out,
                    int id) 
         : m_supervised_warps(), m_stats(stats), m_shader(shader),
         m_scoreboard(scoreboard), m_simt_stack(simt), /*m_pipeline_reg(pipe_regs),*/ m_warp(warp),
-        m_sp_out(sp_out),m_dp_out(dp_out),m_sfu_out(sfu_out),m_mem_out(mem_out), m_id(id){}
+        m_sp_out(sp_out),m_dp_out(dp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_mem_out(mem_out), m_id(id){}
     virtual ~scheduler_unit(){}
     virtual void add_supervised_warp_id(int i) {
         m_supervised_warps.push_back(&warp(i));
@@ -406,6 +407,7 @@ protected:
     register_set* m_sp_out;
     register_set* m_dp_out;
     register_set* m_sfu_out;
+    register_set* m_tensor_core_out;
     register_set* m_mem_out;
 
     int m_id;
@@ -419,9 +421,10 @@ public:
                     register_set* sp_out,
 					register_set* dp_out,
                     register_set* sfu_out,
+                    register_set* tensor_core_out,
                     register_set* mem_out,
                     int id )
-	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, mem_out, id ){}
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ){}
 	virtual ~lrr_scheduler () {}
 	virtual void order_warps ();
     virtual void done_adding_supervised_warps() {
@@ -437,9 +440,10 @@ public:
                     register_set* sp_out,
 					register_set* dp_out,
                     register_set* sfu_out,
+                    register_set* tensor_core_out,
                     register_set* mem_out,
                     int id )
-	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, mem_out, id ){}
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ){}
 	virtual ~gto_scheduler () {}
 	virtual void order_warps ();
     virtual void done_adding_supervised_warps() {
@@ -456,9 +460,10 @@ public:
                     register_set* sp_out,
 					register_set* dp_out,
                     register_set* sfu_out,
+                          register_set* tensor_core_out,
                     register_set* mem_out,
                     int id )
-	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, mem_out, id ){}
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ){}
 	virtual ~oldest_scheduler () {}
 	virtual void order_warps ();
         virtual void done_adding_supervised_warps() {
@@ -475,10 +480,11 @@ public:
                           register_set* sp_out,
 						  register_set* dp_out,
                           register_set* sfu_out,
+                          register_set* tensor_core_out,
                           register_set* mem_out,
                           int id,
                           char* config_str )
-	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, mem_out, id ),
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ),
 	  m_pending_warps() 
     {
         unsigned inner_level_readin;
@@ -526,6 +532,7 @@ public:
                     register_set* sp_out,
 					register_set* dp_out,
                     register_set* sfu_out,
+                    register_set* tensor_core_out,
                     register_set* mem_out,
                     int id,
                     char* config_string );
@@ -1112,6 +1119,23 @@ public:
     virtual void issue(  register_set& source_reg );
 };
 
+class tensor_core : public pipelined_simd_unit
+{
+public:
+    tensor_core( register_set* result_port, const shader_core_config *config, shader_core_ctx *core );
+    virtual bool can_issue( const warp_inst_t &inst ) const
+    {
+        switch(inst.op) {
+        case TENSOR_CORE_OP: break;
+        default: return false;
+        }
+        return pipelined_simd_unit::can_issue(inst);
+    }
+    virtual void active_lanes_in_pipeline();
+    virtual void issue(  register_set& source_reg );
+};
+
+
 class sp_unit : public pipelined_simd_unit
 {
 public:
@@ -1121,7 +1145,9 @@ public:
         switch(inst.op) {
         case SFU_OP: return false; 
         case LOAD_OP: return false;
+        case TENSOR_CORE_LOAD_OP: return false;
         case STORE_OP: return false;
+        case TENSOR_CORE_STORE_OP: return false;
         case MEMORY_BARRIER_OP: return false;
         case DP_OP: return false;
         default: break;
@@ -1165,7 +1191,9 @@ public:
     {
         switch(inst.op) {
         case LOAD_OP: break;
+        case TENSOR_CORE_LOAD_OP: break;
         case STORE_OP: break;
+        case TENSOR_CORE_STORE_OP: break;
         case MEMORY_BARRIER_OP: break;
         default: return false;
         }
@@ -1264,8 +1292,10 @@ enum pipeline_stage_name_t {
     OC_EX_SFU,
     OC_EX_MEM,
     EX_WB,
+    ID_OC_TENSOR_CORE,  
+    OC_EX_TENSOR_CORE,
     N_PIPELINE_STAGES 
-};
+    };
 
 const char* const pipeline_stage_name_decode[] = {
     "ID_OC_SP",
@@ -1277,6 +1307,8 @@ const char* const pipeline_stage_name_decode[] = {
     "OC_EX_SFU",
     "OC_EX_MEM",
     "EX_WB",
+    "ID_OC_TENSOR_CORE",  
+    "OC_EX_TENSOR_CORE",
     "N_PIPELINE_STAGES" 
 };
 
@@ -1299,16 +1331,24 @@ struct shader_core_config : public core_config
 	char* toks = new char[100];
 	char* tokd = toks;
 	strcpy(toks,pipeline_widths_string);
-
+                                  
 	toks = strtok(toks,",");
-	for (unsigned i = 0; i < N_PIPELINE_STAGES; i++) { 
+
+	/*	Removing the tensorcore pipeline while reading the config files if the tensor core is not available.
+	 	If we won't remove it, old regression will be broken.
+		So to support the legacy config files it's best to handle in this way.
+         */  
+	int num_config_to_read=N_PIPELINE_STAGES-2*(!gpgpu_tensor_core_avail);
+
+        for (unsigned i = 0; i <num_config_to_read; i++) { 
 	    assert(toks);
 	    ntok = sscanf(toks,"%d", &pipe_widths[i]);
 	    assert(ntok == 1); 
 	    toks = strtok(NULL,",");
 	}
-	delete[] tokd;
 
+	delete[] tokd;
+	
         if (n_thread_per_shader > MAX_THREAD_PER_SM) {
            printf("GPGPU-Sim uArch: Error ** increase MAX_THREAD_PER_SM in abstract_hardware_model.h from %u to %u\n", 
                   MAX_THREAD_PER_SM, n_thread_per_shader);
@@ -1318,7 +1358,14 @@ struct shader_core_config : public core_config
         assert( !(n_thread_per_shader % warp_size) );
         max_sfu_latency = 512;
         max_sp_latency = 32;
-        m_L1I_config.init(m_L1I_config.m_config_string,FuncCachePreferNone);
+        
+	max_tensor_core_latency = 64;
+        gpgpu_num_tensor_core_units=4;//It will be (#TENSORCORE INSIDE SM)/2 (One warp is allocated to 2 Tensor Core)
+        gpgpu_operand_collector_num_units_tensor_core=24;
+        gpgpu_operand_collector_num_in_ports_tensor_core=8;
+        gpgpu_operand_collector_num_out_ports_tensor_core=8;
+        
+	m_L1I_config.init(m_L1I_config.m_config_string,FuncCachePreferNone);
         m_L1T_config.init(m_L1T_config.m_config_string,FuncCachePreferNone);
         m_L1C_config.init(m_L1C_config.m_config_string,FuncCachePreferNone);
         m_L1D_config.init(m_L1D_config.m_config_string,FuncCachePreferNone);
@@ -1364,24 +1411,29 @@ struct shader_core_config : public core_config
     int gpgpu_operand_collector_num_units_sp;
     int gpgpu_operand_collector_num_units_dp;
     int gpgpu_operand_collector_num_units_sfu;
+    int gpgpu_operand_collector_num_units_tensor_core;
     int gpgpu_operand_collector_num_units_mem;
     int gpgpu_operand_collector_num_units_gen;
 
     unsigned int gpgpu_operand_collector_num_in_ports_sp;
     unsigned int gpgpu_operand_collector_num_in_ports_dp;
     unsigned int gpgpu_operand_collector_num_in_ports_sfu;
+    unsigned int gpgpu_operand_collector_num_in_ports_tensor_core;
     unsigned int gpgpu_operand_collector_num_in_ports_mem;
     unsigned int gpgpu_operand_collector_num_in_ports_gen;
 
     unsigned int gpgpu_operand_collector_num_out_ports_sp;
     unsigned int gpgpu_operand_collector_num_out_ports_dp;
     unsigned int gpgpu_operand_collector_num_out_ports_sfu;
+    unsigned int gpgpu_operand_collector_num_out_ports_tensor_core;
     unsigned int gpgpu_operand_collector_num_out_ports_mem;
     unsigned int gpgpu_operand_collector_num_out_ports_gen;
 
     int gpgpu_num_sp_units;
+    int gpgpu_tensor_core_avail;
     int gpgpu_num_dp_units;
     int gpgpu_num_sfu_units;
+    int gpgpu_num_tensor_core_units;
     int gpgpu_num_mem_units;
 
     //Shader core resources
@@ -1395,6 +1447,7 @@ struct shader_core_config : public core_config
     
     unsigned max_sp_latency;
     unsigned max_sfu_latency;
+    unsigned max_tensor_core_latency;
     
     unsigned n_simt_cores_per_cluster;
     unsigned n_simt_clusters;
@@ -1436,12 +1489,14 @@ struct shader_core_stats_pod {
     unsigned *m_num_fpdiv_acesses;
     unsigned *m_num_sp_acesses;
     unsigned *m_num_sfu_acesses;
+    unsigned *m_num_tensor_core_acesses;
     unsigned *m_num_trans_acesses;
     unsigned *m_num_mem_acesses;
     unsigned *m_num_sp_committed;
     unsigned *m_num_tlb_hits;
     unsigned *m_num_tlb_accesses;
     unsigned *m_num_sfu_committed;
+    unsigned *m_num_tensor_core_committed;
     unsigned *m_num_mem_committed;
     unsigned *m_read_regfile_acesses;
     unsigned *m_write_regfile_acesses;
@@ -1450,12 +1505,14 @@ struct shader_core_stats_pod {
     unsigned *m_num_imul32_acesses;
     unsigned *m_active_sp_lanes;
     unsigned *m_active_sfu_lanes;
+    unsigned *m_active_tensor_core_lanes;
     unsigned *m_active_fu_lanes;
     unsigned *m_active_fu_mem_lanes;
     unsigned *m_n_diverge;    // number of divergence occurring in this shader
     unsigned gpgpu_n_load_insn;
     unsigned gpgpu_n_store_insn;
     unsigned gpgpu_n_shmem_insn;
+    unsigned gpgpu_n_sstarr_insn;
     unsigned gpgpu_n_tex_insn;
     unsigned gpgpu_n_const_insn;
     unsigned gpgpu_n_param_insn;
@@ -1522,6 +1579,7 @@ public:
         m_num_fpdiv_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_sp_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_sfu_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
+        m_num_tensor_core_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_trans_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_mem_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_sp_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
@@ -1529,9 +1587,11 @@ public:
         m_num_tlb_accesses=(unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_active_sp_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_active_sfu_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
+        m_active_tensor_core_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_active_fu_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_active_fu_mem_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_sfu_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
+        m_num_tensor_core_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_mem_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_read_regfile_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_write_regfile_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));