Cleaning up the interconnection core to memory partition statistics

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15745]

4 files changed, 11 insertions, 49 deletions

diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index 2334bf7..a687965 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -335,7 +335,6 @@ void baseline_cache::cycle(){
         if ( !m_memport->full(mf->get_data_size(),mf->get_is_write()) ) {
             m_miss_queue.pop_front();
             m_memport->push(mf);
-            n_simt_to_mem+=mf->get_num_flits(true); // Interconnect power stats
         }
     }
 }
@@ -711,7 +710,6 @@ void tex_cache::cycle(){
         if ( !m_memport->full(mf->get_ctrl_size(),false) ) {
             m_request_fifo.pop();
             m_memport->push(mf);
-            n_simt_to_mem+=mf->get_num_flits(true); // Interconnect power stats
         }
     }
     // read ready lines from cache
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 6dce6b4..65183e4 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -425,7 +425,6 @@ public:
         m_write_access=0;
         m_read_miss=0;
         m_write_miss=0;
-        n_simt_to_mem=0;
     }
 
     virtual ~baseline_cache()
@@ -460,10 +459,6 @@ public:
     	m_tag_array->get_stats(accesses, misses);
     }
 
-    void set_icnt_power_stats(unsigned &simt_to_mem) const{
-    	simt_to_mem = n_simt_to_mem;
-    }
-
 protected:
     // Constructor that can be used by derived classes with custom tag arrays
     baseline_cache( const char *name,
@@ -524,8 +519,6 @@ protected:
     unsigned m_write_access;
     unsigned m_read_miss;
     unsigned m_write_miss;
-
-    unsigned n_simt_to_mem; // Interconnect power stats
 };
 
 /// Read only cache
@@ -703,7 +696,6 @@ public:
         m_cache = new data_block[ config.get_num_lines() ];
         m_request_queue_status = request_status;
         m_rob_status = rob_status;
-        n_simt_to_mem=0;
     }
 
     /// Access function for tex_cache
@@ -725,11 +717,7 @@ public:
     	m_tags.get_stats(accesses, misses);
     }
 
-    void set_icnt_power_stats(unsigned &simt_to_mem) const{
-    	simt_to_mem = n_simt_to_mem;
-    }
-
-    private:
+private:
     std::string m_name;
     const cache_config &m_config;
 
@@ -855,9 +843,6 @@ public:
     typedef std::map<mem_fetch*,extra_mf_fields> extra_mf_fields_lookup;
 
     extra_mf_fields_lookup m_extra_mf_fields;
-
-    // Interconnect power stats
-    unsigned n_simt_to_mem;
 };
 
 #endif
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 797ebc0..d38f300 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1179,23 +1179,6 @@ void ldst_unit::set_stats(){
 	}
 }
 
-void ldst_unit::set_icnt_power_stats(unsigned &simt_to_mem) const{
-	unsigned l1d=0;
-	unsigned tex=0;
-	unsigned l1c=0;
-
-	if( m_L1D ) {
-		m_L1D->set_icnt_power_stats(l1d);
-	}
-	if( m_L1T ){
-		m_L1T->set_icnt_power_stats(tex);
-	}
-	if( m_L1C ){
-		m_L1C->set_icnt_power_stats(l1c);
-	}
-	simt_to_mem = n_simt_to_mem+l1d+tex+l1c; // All components that push packets into the interconnect
-}
-
 void shader_core_ctx::warp_inst_complete(const warp_inst_t &inst)
 {
    #if 0
@@ -1383,7 +1366,6 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea
        } else {
            mem_fetch *mf = m_mf_allocator->alloc(inst,access);
            m_icnt->push(mf);
-           n_simt_to_mem+=mf->get_num_flits(true); // Interconnect power stats (# of flits sent to the memory partitions)
            inst.accessq_pop_back();
            //inst.clear_active( access.get_warp_mask() );
            if( inst.is_load() ) { 
@@ -1548,7 +1530,6 @@ void ldst_unit::init( mem_fetch_interface *icnt,
     m_mem_rc = NO_RC_FAIL;
     m_num_writeback_clients=5; // = shared memory, global/local (uncached), L1D, L1T, L1C
     m_writeback_arb = 0;
-    n_simt_to_mem = 0;
     m_next_global=NULL;
     m_last_inst_gpu_sim_cycle=0;
     m_last_inst_gpu_tot_sim_cycle=0;
@@ -2641,13 +2622,7 @@ void shader_core_ctx::get_cache_stats(unsigned &read_accesses, unsigned &write_a
 }
 
 void shader_core_ctx::set_icnt_power_stats(unsigned &n_simt_to_mem) const{
-	unsigned l1i=0;
-	if( m_L1I ){
-		m_L1I->set_icnt_power_stats(l1i);
-	}
-	m_ldst_unit->set_icnt_power_stats(n_simt_to_mem);
-
-	n_simt_to_mem+=l1i; // l1i + l1d + l1c + l1t + any non-cached access
+	n_simt_to_mem += m_stats->n_simt_to_mem[m_sid];
 }
 
 bool shd_warp_t::functional_done() const
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index fd1cb88..c3420e6 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1082,8 +1082,6 @@ public:
     void get_cache_stats(unsigned &read_accesses, unsigned &write_accesses, unsigned &read_misses, unsigned &write_misses, unsigned cache_type);
     void set_stats();
 
-    void set_icnt_power_stats(unsigned &simt_to_mem) const;
-
 protected:
     ldst_unit( mem_fetch_interface *icnt,
                shader_core_mem_fetch_allocator *mf_allocator,
@@ -1148,9 +1146,6 @@ protected:
    // for debugging
    unsigned long long m_last_inst_gpu_sim_cycle;
    unsigned long long m_last_inst_gpu_tot_sim_cycle;
-
-   // Interconnect power stats
-   unsigned n_simt_to_mem;
 };
 
 enum pipeline_stage_name_t {
@@ -1380,6 +1375,8 @@ struct shader_core_stats_pod {
     unsigned *l1d_write_access;		// L1 Data cache write access
     unsigned *l1d_write_miss;		// L1 Data cache write miss
 
+    unsigned *n_simt_to_mem; // Interconnect power stats
+
 };
 
 class shader_core_stats : public shader_core_stats_pod {
@@ -1441,6 +1438,8 @@ public:
         l1d_write_access = (unsigned *)calloc(config->num_shader(), sizeof(unsigned));
         l1d_write_miss = (unsigned *)calloc(config->num_shader(), sizeof(unsigned));
 
+        n_simt_to_mem = (unsigned *)calloc(config->num_shader(), sizeof(unsigned));
+
         gpgpu_n_shmem_bank_access = (unsigned *)calloc(config->num_shader(), sizeof(unsigned));
 
         m_shader_dynamic_warp_issue_distro.resize( config->num_shader() );
@@ -1692,6 +1691,9 @@ public:
 	 void incsfuactivelanes_stat(unsigned active_count) {m_stats->m_active_sfu_lanes[m_sid]=m_stats->m_active_sfu_lanes[m_sid]+active_count;}
 	 void incfuactivelanes_stat(unsigned active_count) {m_stats->m_active_fu_lanes[m_sid]=m_stats->m_active_fu_lanes[m_sid]+active_count;}
 	 void incfumemactivelanes_stat(unsigned active_count) {m_stats->m_active_fu_mem_lanes[m_sid]=m_stats->m_active_fu_mem_lanes[m_sid]+active_count;}
+
+	 void inc_simt_to_mem(unsigned n_flits){ m_stats->n_simt_to_mem[m_sid] += n_flits; }
+
 private:
 	 unsigned inactive_lanes_accesses_sfu(unsigned active_count,double latency){
       return  ( ((32-active_count)>>1)*latency) + ( ((32-active_count)>>3)*latency) + ( ((32-active_count)>>3)*latency);
@@ -1852,6 +1854,7 @@ public:
     virtual void push(mem_fetch *mf) 
     {
         m_cluster->icnt_inject_request_packet(mf);
+        m_core->inc_simt_to_mem(mf->get_num_flits(true));
     }
 private:
     shader_core_ctx *m_core;
@@ -1872,6 +1875,7 @@ public:
         if ( mf && mf->isatomic() )
             mf->do_atomic(); // execute atomic inside the "memory subsystem"
         m_cluster->push_response_fifo(mf);
+        m_core->inc_simt_to_mem(mf->get_num_flits(true));
     }
 private:
     shader_core_ctx *m_core;