add simple simd lane set partitioning

3 files changed, 59 insertions, 1 deletions

diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 1f7de38..17c7247 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -674,6 +674,14 @@ void shader_core_config::reg_options(class OptionParser *opp) {
                          &reg_file_port_throughput,
                          "the number ports of the register file", "1");
 
+  // SIMD lane partitioning options
+  option_parser_register(
+      opp, "-gpgpu_simd_partitioning", OPT_BOOL, &gpgpu_simd_partitioning,
+      "Enable SIMD lane partitioning into sets (default = disabled)", "0");
+  option_parser_register(
+      opp, "-gpgpu_num_simd_sets", OPT_UINT32, &gpgpu_num_simd_sets,
+      "Number of SIMD sets to partition lanes into (default = 1)", "1");
+
   for (unsigned j = 0; j < SPECIALIZED_UNIT_NUM; ++j) {
     std::stringstream ss;
     ss << "-specialized_unit_" << j + 1;
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index bcf38d3..9f92215 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1052,8 +1052,35 @@ void shader_core_ctx::fetch() {
   m_L1I->cycle();
 }
 
+void exec_shader_core_ctx::execute_warp_inst_per_set(warp_inst_t &inst) {
+  // Execute each SIMD set's threads independently
+  const std::vector<simd_set_info> &sets = inst.get_simd_sets();
+  unsigned warp_id = inst.warp_id();
+  unsigned set_width = m_config->simd_set_width;
+
+  for (unsigned s = 0; s < sets.size(); s++) {
+    const simd_set_info &set = sets[s];
+    if (!set.valid) continue;
+
+    // Execute each active thread in this set
+    for (unsigned lane = 0; lane < set_width; lane++) {
+      if (set.set_active_mask.test(lane)) {
+        unsigned t = set.thread_ids[lane];  // original thread position (0-31)
+        unsigned hw_tid = m_warp_size * warp_id + t;
+        assert(inst.active(t));  // thread must be active in original mask
+        m_thread[hw_tid]->ptx_exec_inst(inst, t);
+        checkExecutionStatusAndUpdate(inst, t, hw_tid);
+      }
+    }
+  }
+}
+
 void exec_shader_core_ctx::func_exec_inst(warp_inst_t &inst) {
-  execute_warp_inst_t(inst);
+  if (m_config->gpgpu_simd_partitioning && inst.has_simd_sets()) {
+    execute_warp_inst_per_set(inst);
+  } else {
+    execute_warp_inst_t(inst);
+  }
   if (inst.is_load() || inst.is_store()) {
     inst.generate_mem_accesses();
     // inst.print_m_accessq();
@@ -1076,6 +1103,11 @@ void shader_core_ctx::issue_warp(register_set &pipe_reg_set,
       m_warp[warp_id]->get_dynamic_warp_id(), sch_id,
       m_warp[warp_id]->get_streamID());  // dynamic instruction information
   m_stats->shader_cycle_distro[2 + (*pipe_reg)->active_count()]++;
+  // Compute SIMD set assignments before functional execution
+  if (m_config->gpgpu_simd_partitioning) {
+    (*pipe_reg)->compute_simd_sets(m_config->gpgpu_num_simd_sets,
+                                   m_config->simd_set_width);
+  }
   func_exec_inst(**pipe_reg);
 
   // Add LDGSTS instructions into a buffer
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index bb2ac33..01dd92c 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1572,6 +1572,18 @@ class shader_core_config : public core_config {
     max_warps_per_shader = n_thread_per_shader / warp_size;
     assert(!(n_thread_per_shader % warp_size));
 
+    // Validate and compute SIMD partitioning derived values
+    if (gpgpu_simd_partitioning) {
+      assert(gpgpu_num_simd_sets > 0 && gpgpu_num_simd_sets <= warp_size);
+      assert(warp_size % gpgpu_num_simd_sets == 0);
+      simd_set_width = warp_size / gpgpu_num_simd_sets;
+      printf("SIMD Partitioning: %u sets of %u lanes\n", gpgpu_num_simd_sets,
+             simd_set_width);
+    } else {
+      gpgpu_num_simd_sets = 1;
+      simd_set_width = warp_size;
+    }
+
     set_pipeline_latency();
 
     m_L1I_config.init(m_L1I_config.m_config_string, FuncCachePreferNone);
@@ -1714,6 +1726,11 @@ class shader_core_config : public core_config {
   unsigned max_dp_latency;
   unsigned max_tensor_core_latency;
 
+  // SIMD lane partitioning
+  bool gpgpu_simd_partitioning;
+  unsigned gpgpu_num_simd_sets;
+  unsigned simd_set_width;  // derived: warp_size / num_simd_sets
+
   unsigned n_simt_cores_per_cluster;
   unsigned n_simt_clusters;
   unsigned n_simt_ejection_buffer_size;
@@ -2630,6 +2647,7 @@ class exec_shader_core_ctx : public shader_core_ctx {
   virtual void checkExecutionStatusAndUpdate(warp_inst_t &inst, unsigned t,
                                              unsigned tid);
   virtual void func_exec_inst(warp_inst_t &inst);
+  void execute_warp_inst_per_set(warp_inst_t &inst);
   virtual unsigned sim_init_thread(kernel_info_t &kernel,
                                    ptx_thread_info **thread_info, int sid,
                                    unsigned tid, unsigned threads_left,