diff options
| author | Inderpreet Singh <[email protected]> | 2012-02-26 03:55:38 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:19:04 -0700 |
| commit | 928f6d330516f03bdbecd52350bf1b9fb9fcf534 (patch) | |
| tree | 24d889a5489298db577782079347eae64aa97c8b /src/gpgpu-sim | |
| parent | dc51fed5c95016d2d7dfd258e955d238586c9a29 (diff) | |
Added fixed latency queue for modeling DRAM latency
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11521]
Diffstat (limited to 'src/gpgpu-sim')
| -rw-r--r-- | src/gpgpu-sim/l2cache.cc | 12 | ||||
| -rw-r--r-- | src/gpgpu-sim/l2cache.h | 10 | ||||
| -rw-r--r-- | src/gpgpu-sim/mem_fetch_status.tup | 1 |
3 files changed, 22 insertions, 1 deletions
diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index 9bee822..6a39b42 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -318,7 +318,19 @@ void memory_partition_unit::dram_cycle() m_dram->dram_log(SAMPLELOG); if( !m_dram->full() && !m_L2_dram_queue->empty() ) { + // L2->DRAM queue to DRAM latency queue mem_fetch *mf = m_L2_dram_queue->pop(); + dram_delay_t d; + d.req = mf; + d.ready_cycle = gpu_sim_cycle+gpu_tot_sim_cycle + 200; + m_dram_latency_queue.push(d); + mf->set_status(IN_PARTITION_DRAM_LATENCY_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); + } + + // DRAM latency queue + if( !m_dram_latency_queue.empty() && ( (gpu_sim_cycle+gpu_tot_sim_cycle) >= m_dram_latency_queue.front().ready_cycle ) && !m_dram->full() ) { + mem_fetch* mf = m_dram_latency_queue.front().req; + m_dram_latency_queue.pop(); m_dram->push(mf); } } diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 12663bd..22640b8 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -92,7 +92,15 @@ private: unsigned long long ready_cycle; class mem_fetch* req; }; - std::queue<rop_delay_t> m_rop; + std::queue<rop_delay_t> m_rop; + + // model DRAM access scheduler latency (fixed latency between L2 and DRAM) + struct dram_delay_t + { + unsigned long long ready_cycle; + class mem_fetch* req; + }; + std::queue<dram_delay_t> m_dram_latency_queue; // these are various FIFOs between units within a memory partition fifo_pipeline<mem_fetch> *m_icnt_L2_queue; diff --git a/src/gpgpu-sim/mem_fetch_status.tup b/src/gpgpu-sim/mem_fetch_status.tup index df8e375..2bfc4dd 100644 --- a/src/gpgpu-sim/mem_fetch_status.tup +++ b/src/gpgpu-sim/mem_fetch_status.tup @@ -75,6 +75,7 @@ MF_TUP_BEGIN( mem_fetch_status ) MF_TUP( IN_PARTITION_ROP_DELAY ), MF_TUP( IN_PARTITION_ICNT_TO_L2_QUEUE ), MF_TUP( IN_PARTITION_L2_TO_DRAM_QUEUE ), + MF_TUP( IN_PARTITION_DRAM_LATENCY_QUEUE ), MF_TUP( IN_PARTITION_L2_MISS_QUEUE ), MF_TUP( IN_PARTITION_MC_INTERFACE_QUEUE ), MF_TUP( IN_PARTITION_MC_INPUT_QUEUE ), |