Add additional formatting pass on directories

4 files changed, 13 insertions, 13 deletions

diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 9b9898e..9fe14ca 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -1312,9 +1312,9 @@ class baseline_cache : public cache_t {
     const cache_config &m_config;
 
     int m_data_port_occupied_cycles;  //< Number of cycle that the data port
-                                      //remains used
+                                      // remains used
     int m_fill_port_occupied_cycles;  //< Number of cycle that the fill port
-                                      //remains used
+                                      // remains used
   };
 
   bandwidth_management m_bandwidth_management;
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index 40c4482..a24ceea 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -264,11 +264,11 @@ class memory_config {
                    // GDDR5 this is identical to RTPS, if for other DRAM this is
                    // different, you will need to split them in two
 
-  unsigned tCCD;  // column to column delay
-  unsigned tRRD;  // minimal time required between activation of rows in
-                  // different banks
-  unsigned tRCD;  // row to column delay - time required to activate a row
-                  // before a read
+  unsigned tCCD;    // column to column delay
+  unsigned tRRD;    // minimal time required between activation of rows in
+                    // different banks
+  unsigned tRCD;    // row to column delay - time required to activate a row
+                    // before a read
   unsigned tRCDWR;  // row to column delay for a write command
   unsigned tRAS;    // time needed to activate row
   unsigned tRP;     // row precharge ie. deactivate row
@@ -276,7 +276,7 @@ class memory_config {
       tRC;  // row cycle time ie. precharge current, then activate different row
   unsigned tCDLR;  // Last data-in to Read command (switching from write to
                    // read)
-  unsigned tWR;  // Last data-in to Row precharge
+  unsigned tWR;    // Last data-in to Row precharge
 
   unsigned CL;    // CAS latency
   unsigned WL;    // WRITE latency
@@ -628,9 +628,9 @@ class gpgpu_sim : public gpgpu_t {
   std::map<unsigned, watchpoint_event> g_watchpoint_hits;
 
   std::string executed_kernel_info_string();  //< format the kernel information
-                                              //into a string for stat printout
+                                              // into a string for stat printout
   void clear_executed_kernel_info();  //< clear the kernel information after
-                                      //stat printout
+                                      // stat printout
 
  public:
   unsigned long long gpu_sim_insn;
diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h
index 21c15ee..d733218 100644
--- a/src/gpgpu-sim/mem_latency_stat.h
+++ b/src/gpgpu-sim/mem_latency_stat.h
@@ -90,8 +90,8 @@ class memory_stats_t {
   unsigned int **totalbankreads;     // bankreads[dram chip id][bank id]
   unsigned int **totalbankaccesses;  // bankaccesses[dram chip id][bank id]
   unsigned int *num_MCBs_accessed;   // tracks how many memory controllers are
-                                    // accessed whenever any thread in a warp
-                                    // misses in cache
+                                     // accessed whenever any thread in a warp
+                                     // misses in cache
   unsigned int *position_of_mrq_chosen;  // position of mrq in m_queue chosen
 
   unsigned ***mem_access_type_stats;  // dram access type classification
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 73ea8b3..fc1c1e2 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -3460,7 +3460,7 @@ void shader_core_ctx::warp_exit(unsigned warp_id) {
   for (unsigned i = warp_id * get_config()->warp_size;
        i < (warp_id + 1) * get_config()->warp_size; i++) {
     //		if(this->m_thread[i]->m_functional_model_thread_state &&
-    //this->m_thread[i].m_functional_model_thread_state->donecycle()==0) {
+    // this->m_thread[i].m_functional_model_thread_state->donecycle()==0) {
     //			done = false;
     //		}