Making the perf sim copy optional, getting rid of an assert that will happen with the new hack and incrementing the cycle so that cudamemcopies take some time (if we don't do this the LRU in the cache does not work)

3 files changed, 18 insertions, 12 deletions

diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index 37fc5ea..e1e41a5 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -324,7 +324,7 @@ void tag_array::fill( new_addr_type addr, unsigned time, mem_access_sector_mask_
     //assert( m_config.m_alloc_policy == ON_FILL );
     unsigned idx;
     enum cache_request_status status = probe(addr,idx,mask);
-    assert(status==MISS||status==SECTOR_MISS); // MSHR should have prevented redundant memory request
+    //assert(status==MISS||status==SECTOR_MISS); // MSHR should have prevented redundant memory request
     if(status==MISS)
     	m_lines[idx]->allocate( m_config.tag(addr), m_config.block_addr(addr), time, mask );
     else if (status==SECTOR_MISS) {
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 263cbad..438769f 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -140,6 +140,8 @@ void power_config::reg_options(class OptionParser * opp)
 
 void memory_config::reg_options(class OptionParser * opp)
 {
+    option_parser_register(opp, "-perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy, 
+                                "Fill the L2 cache on memcpy", "0");
     option_parser_register(opp, "-gpgpu_dram_scheduler", OPT_INT32, &scheduler_type, 
                                 "0 = fifo, 1 = FR-FCFS (defaul)", "1");
     option_parser_register(opp, "-gpgpu_dram_partition_queues", OPT_CSTR, &gpgpu_L2_queue_config, 
@@ -1598,17 +1600,20 @@ void shader_core_ctx::dump_warp_state( FILE *fout ) const
 
 void gpgpu_sim::memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t count )
 {
-    assert (dst_start_addr % 32 == 0);
-    // Right now - I am just going to assume you write the whole last cache line...
-//    assert (count % 128 == 0);
-    for ( unsigned counter = 0; counter < count; counter += 32 ) {
-        const size_t wr_addr = dst_start_addr + counter;
-        addrdec_t raw_addr;
-        mem_access_sector_mask_t mask;
-        mask.set(wr_addr % 128 / 32);
-        m_memory_config->m_address_mapping.addrdec_tlx( wr_addr, &raw_addr );
-        const unsigned partition_id = raw_addr.sub_partition / m_memory_config->m_n_sub_partition_per_memory_channel;
-        m_memory_partition_unit[ partition_id ]->handle_memcpy_to_gpu( wr_addr, raw_addr.sub_partition, mask );
+    if (m_memory_config->m_perf_sim_memcpy) {
+       assert (dst_start_addr % 32 == 0);
+       // Right now - I am just going to assume you write the whole last cache line...
+   //    assert (count % 128 == 0);
+       for ( unsigned counter = 0; counter < count; counter += 32 ) {
+           const size_t wr_addr = dst_start_addr + counter;
+           addrdec_t raw_addr;
+           mem_access_sector_mask_t mask;
+           mask.set(wr_addr % 128 / 32);
+           m_memory_config->m_address_mapping.addrdec_tlx( wr_addr, &raw_addr );
+           const unsigned partition_id = raw_addr.sub_partition / m_memory_config->m_n_sub_partition_per_memory_channel;
+           m_memory_partition_unit[ partition_id ]->handle_memcpy_to_gpu( wr_addr, raw_addr.sub_partition, mask );
+           gpu_sim_cycle += 1;
+       }
     }
 }
 
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index 6382adf..81f13cb 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -290,6 +290,7 @@ struct memory_config {
    unsigned gpgpu_frfcfs_dram_write_queue_size;
    unsigned write_high_watermark;
    unsigned write_low_watermark;
+   bool m_perf_sim_memcpy;
 };
 
 // global counters and flags (please try not to add to this list!!!)