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authorAaron Barnes <[email protected]>2021-05-10 22:45:02 -0400
committerAaron Barnes <[email protected]>2021-05-10 22:45:02 -0400
commite2b410dd117b11098e6bb88be36293afbeb5c444 (patch)
treee7373c78e4cfb7b6ccf35a762f0bb96f3a2a7450 /src/gpgpu-sim
parent4825a1dad0938a40c8feb01e554ca8f5fdc6c4c5 (diff)
clean up redundant method args
Diffstat (limited to 'src/gpgpu-sim')
-rw-r--r--src/gpgpu-sim/shader.cc13
-rw-r--r--src/gpgpu-sim/shader.h4
2 files changed, 7 insertions, 10 deletions
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index acd41d8..e3a3e9c 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -3968,10 +3968,7 @@ void opndcoll_rfu_t::dispatch_ready_cu() {
m_shader->get_config()->warp_size); // cu->get_active_count());
}
}
- unsigned reg_id;
- if (sub_core_model)
- reg_id = cu->get_reg_id();
- cu->dispatch(sub_core_model, reg_id);
+ cu->dispatch();
}
}
}
@@ -4055,8 +4052,8 @@ void opndcoll_rfu_t::allocate_reads() {
}
}
-bool opndcoll_rfu_t::collector_unit_t::ready(bool sub_core_model, unsigned reg_id) const {
- return (!m_free) && m_not_ready.none() && (*m_output_register).has_free(sub_core_model, reg_id);
+bool opndcoll_rfu_t::collector_unit_t::ready() const {
+ return (!m_free) && m_not_ready.none() && (*m_output_register).has_free(m_sub_core_model, m_reg_id);
}
void opndcoll_rfu_t::collector_unit_t::dump(
@@ -4121,7 +4118,7 @@ bool opndcoll_rfu_t::collector_unit_t::allocate(register_set *pipeline_reg_set,
return false;
}
-void opndcoll_rfu_t::collector_unit_t::dispatch(bool sub_core_model, unsigned reg_id) {
+void opndcoll_rfu_t::collector_unit_t::dispatch() {
assert(m_not_ready.none());
// Print out which OC dispatched which warp sched id to which exec pipeline
/* std::cout << "Dispatched from OC: "
@@ -4135,7 +4132,7 @@ void opndcoll_rfu_t::collector_unit_t::dispatch(bool sub_core_model, unsigned re
<< "\treg id: "
<< reg_id
<< std::endl; */
- m_output_register->move_in(sub_core_model, reg_id, m_warp);
+ m_output_register->move_in(m_sub_core_model, m_reg_id, m_warp);
m_free = true;
m_output_register = NULL;
for (unsigned i = 0; i < MAX_REG_OPERANDS * 2; i++) m_src_op[i].reset();
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index a5a8166..00e7deb 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -867,7 +867,7 @@ class opndcoll_rfu_t { // operand collector based register file unit
m_bank_warp_shift = 0;
}
// accessors
- bool ready(bool sub_core_model, unsigned reg_id) const;
+ bool ready() const;
const op_t *get_operands() const { return m_src_op; }
void dump(FILE *fp, const shader_core_ctx *shader) const;
@@ -889,7 +889,7 @@ class opndcoll_rfu_t { // operand collector based register file unit
void collect_operand(unsigned op) { m_not_ready.reset(op); }
unsigned get_num_operands() const { return m_warp->get_num_operands(); }
unsigned get_num_regs() const { return m_warp->get_num_regs(); }
- void dispatch(bool sub_core_model, unsigned reg_id);
+ void dispatch();
bool is_free() { return m_free; }
private: