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authorAhmad Alawneh <[email protected]>2023-06-06 22:58:29 -0400
committerAhmad Alawneh <[email protected]>2023-06-12 20:31:30 -0400
commite700b1816492bb811e5aa12d1b1b0ec778e04235 (patch)
treed5c0ab109525ec80a4b407b02be8d1d2a1540a72 /src/gpgpu-sim
parentce5c443efa2ec72b7d7b88210eea71db89b29c89 (diff)
fix types, change int to unsigned int
Diffstat (limited to 'src/gpgpu-sim')
-rw-r--r--src/gpgpu-sim/gpu-sim.cc14
-rw-r--r--src/gpgpu-sim/shader.cc6
-rw-r--r--src/gpgpu-sim/shader.h14
3 files changed, 17 insertions, 17 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 5a68f13..ea50fa0 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -586,26 +586,26 @@ void shader_core_config::reg_options(class OptionParser *opp) {
"ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_"
"INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE",
"1,1,1,1,1,1,1,1,1,1,1,1,1");
- option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_UINT32,
&gpgpu_tensor_core_avail,
"Tensor Core Available (default=0)", "0");
- option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_sp_units", OPT_UINT32,
&gpgpu_num_sp_units, "Number of SP units (default=1)",
"1");
- option_parser_register(opp, "-gpgpu_num_dp_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_dp_units", OPT_UINT32,
&gpgpu_num_dp_units, "Number of DP units (default=0)",
"0");
- option_parser_register(opp, "-gpgpu_num_int_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_int_units", OPT_UINT32,
&gpgpu_num_int_units,
"Number of INT units (default=0)", "0");
- option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_UINT32,
&gpgpu_num_sfu_units, "Number of SF units (default=1)",
"1");
- option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_UINT32,
&gpgpu_num_tensor_core_units,
"Number of tensor_core units (default=1)", "0");
option_parser_register(
- opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units,
+ opp, "-gpgpu_num_mem_units", OPT_UINT32, &gpgpu_num_mem_units,
"Number if ldst units (default=1) WARNING: not hooked up to anything",
"1");
option_parser_register(
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 4ae0f62..fdc7f77 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -107,7 +107,7 @@ void shader_core_ctx::create_front_pipeline() {
m_pipeline_reg.push_back(
register_set(m_config->pipe_widths[j], pipeline_stage_name_decode[j]));
}
- for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+ for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
m_pipeline_reg.push_back(
register_set(m_config->m_specialized_unit[j].id_oc_spec_reg_width,
m_config->m_specialized_unit[j].name));
@@ -115,7 +115,7 @@ void shader_core_ctx::create_front_pipeline() {
m_specilized_dispatch_reg.push_back(
&m_pipeline_reg[m_pipeline_reg.size() - 1]);
}
- for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+ for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
m_pipeline_reg.push_back(
register_set(m_config->m_specialized_unit[j].oc_ex_spec_reg_width,
m_config->m_specialized_unit[j].name));
@@ -140,7 +140,7 @@ void shader_core_ctx::create_front_pipeline() {
if (m_config->gpgpu_num_int_units > 0)
assert(m_config->gpgpu_num_sched_per_core ==
m_pipeline_reg[ID_OC_INT].get_size());
- for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+ for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
if (m_config->m_specialized_unit[j].num_units > 0)
assert(m_config->gpgpu_num_sched_per_core ==
m_config->m_specialized_unit[j].id_oc_spec_reg_width);
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index deea1c9..c486d13 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1622,13 +1622,13 @@ class shader_core_config : public core_config {
unsigned int gpgpu_operand_collector_num_out_ports_gen;
unsigned int gpgpu_operand_collector_num_out_ports_int;
- int gpgpu_num_sp_units;
- int gpgpu_tensor_core_avail;
- int gpgpu_num_dp_units;
- int gpgpu_num_sfu_units;
- int gpgpu_num_tensor_core_units;
- int gpgpu_num_mem_units;
- int gpgpu_num_int_units;
+ unsigned int gpgpu_num_sp_units;
+ unsigned int gpgpu_tensor_core_avail;
+ unsigned int gpgpu_num_dp_units;
+ unsigned int gpgpu_num_sfu_units;
+ unsigned int gpgpu_num_tensor_core_units;
+ unsigned int gpgpu_num_mem_units;
+ unsigned int gpgpu_num_int_units;
// Shader core resources
unsigned gpgpu_shader_registers;