diff options
| author | Nick <[email protected]> | 2019-09-13 07:48:04 -0400 |
|---|---|---|
| committer | Nick <[email protected]> | 2019-09-13 07:48:04 -0400 |
| commit | 96a0ebfc2583e6f92d8287ecd128eb7c634be017 (patch) | |
| tree | d8337c6979b420f5075aeebefcc676b46cf6e639 /src/gpuwattch/iocontrollers.cc | |
| parent | ca563ea85ead434e0d579026b5e66e829af5efe5 (diff) | |
Revert "Add additional formatting pass on directories"
This reverts commit ca563ea85ead434e0d579026b5e66e829af5efe5.
Diffstat (limited to 'src/gpuwattch/iocontrollers.cc')
| -rw-r--r-- | src/gpuwattch/iocontrollers.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/gpuwattch/iocontrollers.cc b/src/gpuwattch/iocontrollers.cc index 6a29add..2425d40 100644 --- a/src/gpuwattch/iocontrollers.cc +++ b/src/gpuwattch/iocontrollers.cc @@ -236,7 +236,7 @@ void NIUController::set_niu_param() { niup.perc_load = XML->sys.niu.total_load_perc; niup.type = XML->sys.niu.type; // niup.executionTime = - // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6); + //XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6); } PCIeController::PCIeController(ParseXML* XML_interface, @@ -276,7 +276,7 @@ PCIeController::PCIeController(ParseXML* XML_interface, 1.1 * (interface_ip.F_sz_nm / 65.0); // //Cadence ChipEstimate using 65nm soft IP; // frontend_dyn = - // 0.27e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0); + //0.27e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0); // SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm SerDer_dyn = 0.01 * 4 * (interface_ip.F_sz_um / 0.09) * g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd / @@ -305,7 +305,7 @@ PCIeController::PCIeController(ParseXML* XML_interface, 1.1 * (interface_ip.F_sz_nm / 65.0); // //Cadence ChipEstimate using 65nm soft IP; // frontend_dyn = - // 0.27e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0); + //0.27e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0); // SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm SerDer_dyn = 0.01 * 4 * (interface_ip.F_sz_um / 0.09) * g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd / @@ -387,7 +387,7 @@ void PCIeController::set_pcie_param() { pciep.type = XML->sys.pcie.type; pciep.withPHY = XML->sys.pcie.withPHY; // pciep.executionTime = - // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6); + //XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6); } FlashController::FlashController(ParseXML* XML_interface, @@ -507,5 +507,5 @@ void FlashController::set_fc_param() { fcp.type = XML->sys.flashc.type; fcp.withPHY = XML->sys.flashc.withPHY; // flashcp.executionTime = - // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6); + //XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6); } |