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| author | Tayler Hetherington <[email protected]> | 2012-09-19 14:51:45 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:49:20 -0700 |
| commit | b09eeed6aa36239f661d6452e996e3e5f8ef5984 (patch) | |
| tree | 1d71f118193e7eb8b8de79d3f08a934067e5a143 /src/intersim/pim.cpp | |
| parent | b19fd89f07b3221ea73f6c2442880c2e5c1e68a5 (diff) | |
Revision #2 of modifying the cache hierarchy.
Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations.
Added WRITE_EVICT cache write policy.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109]
Diffstat (limited to 'src/intersim/pim.cpp')
0 files changed, 0 insertions, 0 deletions