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| author | Mahmoud Khairy A. Abdallah <[email protected]> | 2021-05-19 22:20:56 -0400 |
|---|---|---|
| committer | Mahmoud Khairy A. Abdallah <[email protected]> | 2021-05-19 22:20:56 -0400 |
| commit | 7fac247e3e1c4326081c3ea4d46da6c5dc83ccb9 (patch) | |
| tree | 6f45c4e4450fb53e55834a37fcc8ad7c3ca4210b /src/intersim2/packet_reply_info.cpp | |
| parent | b466afea67e6d6faf49f01ecfe378257fbdb93af (diff) | |
change L1 cache config in Volta+ to be write-through and write-allocate based on recent ubench
Diffstat (limited to 'src/intersim2/packet_reply_info.cpp')
0 files changed, 0 insertions, 0 deletions