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authorTor Aamodt <[email protected]>2010-10-19 23:10:51 -0800
committerTor Aamodt <[email protected]>2010-10-19 23:10:51 -0800
commitee5ea34857e4ecc6c63d4971e549076c6a9888ba (patch)
tree6931d8981a4179b479cfdc43cd3ec3972e754d9d /src/intersim
parent6c65cb0119ca7c84993cab6b8828687e1b331bd0 (diff)
adding texture cache model with fragment fifo for latency hiding
passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7886]
Diffstat (limited to 'src/intersim')
-rw-r--r--src/intersim/interconnect_interface.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intersim/interconnect_interface.cpp b/src/intersim/interconnect_interface.cpp
index b838dcf..40cf00d 100644
--- a/src/intersim/interconnect_interface.cpp
+++ b/src/intersim/interconnect_interface.cpp
@@ -467,7 +467,7 @@ void init_interconnect (char* config_file,
if (icnt_config.GetInt("input_buf_size")) {
input_buffer_capacity = icnt_config.GetInt("input_buf_size");
} else {
- input_buffer_capacity = 8;
+ input_buffer_capacity = 9;
}
create_buf(traffic[0]->_dests,input_buffer_capacity,icnt_config.GetInt( "num_vcs" ));
MATLAB_OUTPUT = icnt_config.GetInt("MATLAB_OUTPUT");