adding turing ISA

2 files changed, 235 insertions, 27 deletions

diff --git a/src/trace-driven/ISA_Def/trace_opcode.h b/src/trace-driven/ISA_Def/trace_opcode.h
index 0badabc..e68be45 100644
--- a/src/trace-driven/ISA_Def/trace_opcode.h
+++ b/src/trace-driven/ISA_Def/trace_opcode.h
@@ -9,7 +9,7 @@
 #include "../../abstract_hardware_model.h"
 
 enum TraceInstrOpcode {
-  // volta (common insts for others cards as well)
+  // Volta (includes common insts for others cards as well)
   OP_FADD = 1,
   OP_FADD32I,
   OP_FCHK,
@@ -165,6 +165,43 @@ enum TraceInstrOpcode {
   OP_PSET,
   OP_VMNMX,
   OP_ISET,
+  // unique insts for turing
+  OP_BMMA,
+  OP_MOVM,
+  OP_LDSM,
+  OP_R2UR,
+  OP_S2UR,
+  OP_UBMSK,
+  OP_UBREV,
+  OP_UCLEA,
+  OP_UFLO,
+  OP_UIADD3,
+  OP_UIMAD,
+  OP_UISETP,
+  OP_ULDC,
+  OP_ULEA,
+  OP_ULOP,
+  OP_ULOP3,
+  OP_ULOP32I,
+  OP_UMOV,
+  OP_UP2UR,
+  OP_UPLOP3,
+  OP_UPOPC,
+  OP_UPRMT,
+  OP_UPSETP,
+  OP_UR2UP,
+  OP_USEL,
+  OP_USGXT,
+  OP_USHF,
+  OP_USHL,
+  OP_USHR,
+  OP_VOTEU,
+  OP_SUATOM,
+  OP_SULD,
+  OP_SURED,
+  OP_SUST,
+  OP_BRXU,
+  OP_JMXU,
   // unique insts for kepler
   OP_FCMP,
   OP_FSWZ,
@@ -181,28 +218,6 @@ enum TraceInstrOpcode {
 };
 typedef enum TraceInstrOpcode sass_op_type;
 
-/*
-enum uarch_op_t {
-   NO_OP=-1,
-   ALU_OP=1,
-   SFU_OP,
-   TENSOR_CORE_OP,
-   DP_OP,
-   SP_OP,
-   INTP_OP,
-   ALU_SFU_OP,
-   LOAD_OP,
-   TENSOR_CORE_LOAD_OP,
-   TENSOR_CORE_STORE_OP,
-   STORE_OP,
-   BRANCH_OP,
-   BARRIER_OP,
-   MEMORY_BARRIER_OP,
-   CALL_OPS,
-   RET_OPS
-};
-typedef enum uarch_op_t op_type;
- */
 
 struct OpcodeChar {
   OpcodeChar(unsigned m_opcode, unsigned m_opcode_category) {
diff --git a/src/trace-driven/ISA_Def/turing_opcode.h b/src/trace-driven/ISA_Def/turing_opcode.h
index 97921ca..0374bdd 100644
--- a/src/trace-driven/ISA_Def/turing_opcode.h
+++ b/src/trace-driven/ISA_Def/turing_opcode.h
@@ -8,15 +8,208 @@
 #include <unordered_map>
 #include "trace_opcode.h"
 
-// TO DO: moving this to a yml or def files
+#define TURING_BINART_VERSION 75
+#define TURING_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000
 
-#define TURING_BINART_VERSION 72
+// TO DO: moving this to a yml or def files
 
-/// Tuing SM_72 ISA
+/// Volta SM_70 ISA
 // see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html
 static const std::unordered_map<std::string, OpcodeChar> Turing_OpcodeMap = {
+    // Floating Point 32 Instructions
+    {"FADD", OpcodeChar(OP_FADD, SP_OP)},
+    {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)},
+    {"FCHK", OpcodeChar(OP_FCHK, SP_OP)},
+    {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)},
+    {"FFMA", OpcodeChar(OP_FFMA, SP_OP)},
+    {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)},
+    {"FMUL", OpcodeChar(OP_FMUL, SP_OP)},
+    {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)},
+    {"FSEL", OpcodeChar(OP_FSEL, SP_OP)},
+    {"FSET", OpcodeChar(OP_FSET, SP_OP)},
+    {"FSETP", OpcodeChar(OP_FSETP, SP_OP)},
+    {"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)},
+    // SFU
+    {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)},
+
+    // Floating Point 16 Instructions
+    {"HADD2", OpcodeChar(OP_HADD2, SP_OP)},
+    {"HADD2_32I", OpcodeChar(OP_HADD2_32I, SP_OP)},
+    {"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)},
+    {"HFMA2_32I", OpcodeChar(OP_HFMA2_32I, SP_OP)},
+    {"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)},
+    {"HMUL2_32I", OpcodeChar(OP_HMUL2_32I, SP_OP)},
+    {"HSET2", OpcodeChar(OP_HSET2, SP_OP)},
+    {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)},
+
+    // Tensor Core Instructions
+    {"HMMA", OpcodeChar(OP_HMMA, TENSOR_CORE_OP)},
+
+    // Double Point Instructions
+    {"DADD", OpcodeChar(OP_DADD, DP_OP)},
+    {"DFMA", OpcodeChar(OP_DFMA, DP_OP)},
+    {"DMUL", OpcodeChar(OP_DMUL, DP_OP)},
+    {"DSETP", OpcodeChar(OP_DSETP, DP_OP)},
+
+    // Integer Instructions
+    {"BMMA", OpcodeChar(OP_BMMA, INTP_OP)},  ////////
+    {"BMSK", OpcodeChar(OP_BMSK, INTP_OP)},
+    {"BREV", OpcodeChar(OP_BREV, INTP_OP)},
+    {"FLO", OpcodeChar(OP_FLO, INTP_OP)},
+    {"IABS", OpcodeChar(OP_IABS, INTP_OP)},
+    {"IADD", OpcodeChar(OP_IADD, INTP_OP)},
+    {"IADD3", OpcodeChar(OP_IADD3, INTP_OP)},
+    {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)},
+    {"IDP", OpcodeChar(OP_IDP, INTP_OP)},
+    {"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)},
+    {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)},
+    {"IMMA", OpcodeChar(OP_IMMA, INTP_OP)},
+    {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)},
+    {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)},
+    {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)},
+    {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)},
+    {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)},
+    {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)},
+    {"LEA", OpcodeChar(OP_LEA, INTP_OP)},
+    {"LOP", OpcodeChar(OP_LOP, INTP_OP)},
+    {"LOP3", OpcodeChar(OP_LOP3, INTP_OP)},
+    {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)},
+    {"POPC", OpcodeChar(OP_POPC, INTP_OP)},
+    {"SHF", OpcodeChar(OP_SHF, INTP_OP)},
+    {"SHL", OpcodeChar(OP_SHL, INTP_OP)},  //////////
+    {"SHR", OpcodeChar(OP_SHR, INTP_OP)},
+    {"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)},
+    {"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)},
+
+    // Conversion Instructions
+    {"F2F", OpcodeChar(OP_F2F, ALU_OP)},
+    {"F2I", OpcodeChar(OP_F2I, ALU_OP)},
+    {"I2F", OpcodeChar(OP_I2F, ALU_OP)},
+    {"I2I", OpcodeChar(OP_I2I, ALU_OP)},
+    {"I2IP", OpcodeChar(OP_I2IP, ALU_OP)},
+    {"FRND", OpcodeChar(OP_FRND, ALU_OP)},
+
+    // Movement Instructions
+    {"MOV", OpcodeChar(OP_MOV, ALU_OP)},
+    {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)},
+    {"MOVM", OpcodeChar(OP_MOVM, ALU_OP)},  // move matrix
+    {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)},
+    {"SEL", OpcodeChar(OP_SEL, ALU_OP)},
+    {"SGXT", OpcodeChar(OP_SGXT, ALU_OP)},
+    {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)},
+
+    // Predicate Instructions
+    {"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)},
+    {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)},
+    {"P2R", OpcodeChar(OP_P2R, ALU_OP)},
+    {"R2P", OpcodeChar(OP_R2P, ALU_OP)},
+
+    // Load/Store Instructions
+    {"LD", OpcodeChar(OP_LD, LOAD_OP)},
+    // For now, we ignore constant loads, consider it as ALU_OP, TO DO
+    {"LDC", OpcodeChar(OP_LDC, ALU_OP)},
+    {"LDG", OpcodeChar(OP_LDG, LOAD_OP)},
+    {"LDL", OpcodeChar(OP_LDL, LOAD_OP)},
+    {"LDS", OpcodeChar(OP_LDS, LOAD_OP)},
+    {"LDSM", OpcodeChar(OP_LDSM, LOAD_OP)},  //
+    {"ST", OpcodeChar(OP_ST, STORE_OP)},
+    {"STG", OpcodeChar(OP_STG, STORE_OP)},
+    {"STL", OpcodeChar(OP_STL, STORE_OP)},
+    {"STS", OpcodeChar(OP_STS, STORE_OP)},
+    {"MATCH", OpcodeChar(OP_MATCH, ALU_OP)},
+    {"QSPC", OpcodeChar(OP_QSPC, ALU_OP)},
+    {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)},
+    {"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)},
+    {"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)},
+    {"RED", OpcodeChar(OP_RED, STORE_OP)},
+    {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)},
+    {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)},
+    {"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)},
+    {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)},
+    {"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)},
+
+    // Uniform Datapath Instruction //
+    {"R2UR", OpcodeChar(OP_R2UR, ALU_OP)},
+    {"S2UR", OpcodeChar(OP_S2UR, ALU_OP)},
+    {"UBMSK", OpcodeChar(OP_UBMSK, ALU_OP)},
+    {"UBREV", OpcodeChar(OP_UBREV, ALU_OP)},
+    {"UCLEA", OpcodeChar(OP_UCLEA, ALU_OP)},
+    {"UFLO", OpcodeChar(OP_UFLO, ALU_OP)},
+    {"UIADD3", OpcodeChar(OP_UIADD3, ALU_OP)},
+    {"UIMAD", OpcodeChar(OP_UIMAD, ALU_OP)},
+    {"UISETP", OpcodeChar(OP_UISETP, ALU_OP)},
+    {"ULDC", OpcodeChar(OP_ULDC, ALU_OP)},
+    {"ULEA", OpcodeChar(OP_ULEA, ALU_OP)},
+    {"ULOP", OpcodeChar(OP_ULOP, ALU_OP)},
+    {"ULOP3", OpcodeChar(OP_ULOP3, ALU_OP)},
+    {"ULOP32I", OpcodeChar(OP_ULOP32I, ALU_OP)},
+    {"UMOV", OpcodeChar(OP_UMOV, ALU_OP)},
+    {"UP2UR", OpcodeChar(OP_UP2UR, ALU_OP)},
+    {"UPLOP3", OpcodeChar(OP_UPLOP3, ALU_OP)},
+    {"UPOPC", OpcodeChar(OP_UPOPC, ALU_OP)},
+    {"UPRMT", OpcodeChar(OP_UPRMT, ALU_OP)},
+    {"UPSETP", OpcodeChar(OP_UPSETP, ALU_OP)},
+    {"UR2UP", OpcodeChar(OP_UR2UP, ALU_OP)},
+    {"USEL", OpcodeChar(OP_USEL, ALU_OP)},
+    {"USGXT", OpcodeChar(OP_USGXT, ALU_OP)},
+    {"USHF", OpcodeChar(OP_USHF, ALU_OP)},
+    {"USHL", OpcodeChar(OP_USHL, ALU_OP)},
+    {"USHR", OpcodeChar(OP_USHR, ALU_OP)},
+    {"VOTEU", OpcodeChar(OP_VOTEU, ALU_OP)},
+
+    // Texture Instructions
+    // For now, we ignore texture loads, consider it as ALU_OP
+    {"TEX", OpcodeChar(OP_TEX, ALU_OP)},
+    {"TLD", OpcodeChar(OP_TLD, ALU_OP)},
+    {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)},
+    {"TMML", OpcodeChar(OP_TMML, ALU_OP)},
+    {"TXD", OpcodeChar(OP_TXD, ALU_OP)},
+    {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)},
+
+    // Surface Instructions //
+    {"SUATOM", OpcodeChar(OP_SUATOM, ALU_OP)},
+    {"SULD", OpcodeChar(OP_SULD, ALU_OP)},
+    {"SURED", OpcodeChar(OP_SURED, ALU_OP)},
+    {"SUST", OpcodeChar(OP_SUST, ALU_OP)},
+
+    // Control Instructions
+    {"BMOV", OpcodeChar(OP_BMOV, BRANCH_OP)},
+    {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)},
+    {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)},
+    {"BREAK", OpcodeChar(OP_BREAK, BRANCH_OP)},
+    {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)},
+    {"BRXU", OpcodeChar(OP_BRXU, BRANCH_OP)},  //
+    {"BSSY", OpcodeChar(OP_BSSY, BRANCH_OP)},
+    {"BSYNC", OpcodeChar(OP_BSYNC, BRANCH_OP)},
+    {"CALL", OpcodeChar(OP_CALL, CALL_OPS)},
+    {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)},
+    {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)},
+    {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)},
+    {"JMXU", OpcodeChar(OP_JMXU, BRANCH_OP)},  ///
+    {"KILL", OpcodeChar(OP_KILL, BRANCH_OP)},
+    {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)},
+    {"RET", OpcodeChar(OP_RET, RET_OPS)},
+    {"RPCMOV", OpcodeChar(OP_RPCMOV, BRANCH_OP)},
+    {"RTT", OpcodeChar(OP_RTT, RET_OPS)},
+    {"WARPSYNC", OpcodeChar(OP_WARPSYNC, BRANCH_OP)},
+    {"YIELD", OpcodeChar(OP_YIELD, BRANCH_OP)},
 
-    // TO fill
+    // Miscellaneous Instructions
+    {"B2R", OpcodeChar(OP_B2R, ALU_OP)},
+    {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)},
+    {"CS2R", OpcodeChar(OP_CS2R, ALU_OP)},
+    {"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)},
+    {"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)},
+    {"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)},
+    {"LEPC", OpcodeChar(OP_LEPC, ALU_OP)},
+    {"NOP", OpcodeChar(OP_NOP, ALU_OP)},
+    {"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)},
+    {"R2B", OpcodeChar(OP_R2B, ALU_OP)},
+    {"S2R", OpcodeChar(OP_S2R, ALU_OP)},
+    {"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)},
+    {"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)},
+    {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)},
+    {"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)},
 
 };