Revived all of the source code view stats except exposed pipeline latency.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11329]

4 files changed, 28 insertions, 3 deletions

diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index ed62177..841be93 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -248,6 +248,7 @@ void warp_inst_t::generate_mem_accesses()
         }
         assert( total_accesses > 0 && total_accesses <= m_config->warp_size );
         cycles = total_accesses; // shared memory conflicts modeled as larger initiation interval 
+        ptx_file_line_stats_add_smem_bank_conflict( pc, total_accesses );
         break;
     }
 
@@ -291,7 +292,9 @@ void warp_inst_t::generate_mem_accesses()
             m_accessq.push_back( mem_access_t(access_type,a->first,cache_block_size,is_write,a->second,byte_mask) );
     }
 
-    ptx_file_line_stats_add_uncoalesced_gmem( pc, m_accessq.size() - starting_queue_size );
+    if ( space.get_type() == global_space ) {
+        ptx_file_line_stats_add_uncoalesced_gmem( pc, m_accessq.size() - starting_queue_size );
+    }
     m_mem_accesses_created=true;
 }
 
@@ -486,6 +489,13 @@ void warp_inst_t::memory_coalescing_arch_13_reduce_and_send( bool is_write, mem_
    m_accessq.push_back( mem_access_t(access_type,addr,size,is_write,info.active,info.bytes) );
 }
 
+void warp_inst_t::completed( unsigned long long cycle )
+{
+   unsigned long long latency = cycle - issue_cycle; 
+   assert(latency <= cycle); // underflow detection 
+   ptx_file_line_stats_add_latency(pc, latency * active_count());  
+}
+
 
 unsigned kernel_info_t::m_next_uid = 1;
 
@@ -597,6 +607,7 @@ void simt_stack::update( simt_mask_t &thread_done, addr_vector_t &next_pc, addre
 
     simt_mask_t  top_active_mask = m_active_mask[stack_top];
     address_type top_recvg_pc = m_recvg_pc[stack_top];
+    address_type top_pc = m_pc[stack_top]; // the pc of the instruction just executed 
 
     assert(top_active_mask.any());
 
@@ -659,6 +670,10 @@ void simt_stack::update( simt_mask_t &thread_done, addr_vector_t &next_pc, addre
 
     assert(m_stack_top >= 0);
     assert(m_stack_top < m_warp_size * 2);
+
+    if (warp_diverged) {
+        ptx_file_line_stats_add_warp_divergence(top_pc, 1); 
+    }
 }
 
 void core_t::execute_warp_inst_t(warp_inst_t &inst, unsigned warpSize, unsigned warpId){
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 229d6a1..3bc7538 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -694,6 +694,7 @@ public:
         m_cache_hit=false;
         m_empty=false;
     }
+    void completed( unsigned long long cycle );  // stat collection: called when the instruction is completed  
     void set_addr( unsigned n, new_addr_type addr ) 
     {
         if( !m_per_scalar_thread_valid ) {
diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc
index b23919e..68cd850 100644
--- a/src/gpgpu-sim/mem_latency_stat.cc
+++ b/src/gpgpu-sim/mem_latency_stat.cc
@@ -181,10 +181,10 @@ void memory_stats_t::memlatstat_dram_access(mem_fetch *mf)
          shader_mem_acc_log( mf->get_sid(), dram_id, bank, 'r');
          totalbankreads[dram_id][bank]++;
       }
-      if (mf->get_pc() != (unsigned)-1) 
-         ptx_file_line_stats_add_dram_traffic(mf->get_pc(),1);
       mem_access_type_stats[mf->get_access_type()][dram_id][bank]++;
    }
+   if (mf->get_pc() != (unsigned)-1) 
+      ptx_file_line_stats_add_dram_traffic(mf->get_pc(), mf->get_data_size());
 }
 
 void memory_stats_t::memlatstat_icnt2mem_pop(mem_fetch *mf)
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 0275757..c06d1e7 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -719,6 +719,7 @@ void shader_core_ctx::writeback()
         m_last_inst_gpu_sim_cycle = gpu_sim_cycle;
         m_last_inst_gpu_tot_sim_cycle = gpu_tot_sim_cycle;
         m_gpu->gpu_sim_insn += pipe_reg->active_count();
+        pipe_reg->completed(gpu_tot_sim_cycle + gpu_sim_cycle); 
         pipe_reg->clear();
     }
 }
@@ -945,6 +946,7 @@ void ldst_unit::writeback()
     // process next instruction that is going to writeback
     if( !m_next_wb.empty() ) {
         if( m_operand_collector->writeback(m_next_wb) ) {
+            bool insn_completed = false; 
             for( unsigned r=0; r < 4; r++ ) {
                 if( m_next_wb.out[r] > 0 ) {
                     if( m_next_wb.space.get_type() != shared_space ) {
@@ -955,14 +957,19 @@ void ldst_unit::writeback()
                             m_scoreboard->releaseRegister( m_next_wb.warp_id(), m_next_wb.out[r] );
                             m_stats->m_num_sim_insn[m_sid]++;
                             m_core->get_gpu()->gpu_sim_insn += m_next_wb.active_count();
+                            insn_completed = true; 
                         }
                     } else { // shared 
                         m_scoreboard->releaseRegister( m_next_wb.warp_id(), m_next_wb.out[r] );
                         m_stats->m_num_sim_insn[m_sid]++;
                         m_core->get_gpu()->gpu_sim_insn += m_next_wb.active_count();
+                        insn_completed = true; 
                     }
                 }
             }
+            if( insn_completed ) {
+                m_next_wb.completed( gpu_tot_sim_cycle + gpu_sim_cycle ); 
+            }
             m_next_wb.clear();
             m_last_inst_gpu_sim_cycle = gpu_sim_cycle;
             m_last_inst_gpu_tot_sim_cycle = gpu_tot_sim_cycle;
@@ -1103,6 +1110,7 @@ void ldst_unit::cycle()
                }
                if( !pending_requests ) {
                    m_core->get_gpu()->gpu_sim_insn += m_dispatch_reg->active_count();
+                   m_dispatch_reg->completed(gpu_tot_sim_cycle + gpu_sim_cycle); 
                    m_scoreboard->releaseRegisters(m_dispatch_reg);
                    m_stats->m_num_sim_insn[m_sid]++;
                }
@@ -1113,6 +1121,7 @@ void ldst_unit::cycle()
            // stores exit pipeline here
            m_core->dec_inst_in_pipeline(warp_id);
            m_core->get_gpu()->gpu_sim_insn += m_dispatch_reg->active_count();
+           m_dispatch_reg->completed(gpu_tot_sim_cycle + gpu_sim_cycle); 
            m_dispatch_reg->clear();
            m_stats->m_num_sim_insn[m_sid]++;
        }