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| author | Mahmoud Khairy A. Abdallah <[email protected]> | 2021-05-19 17:56:14 -0400 |
|---|---|---|
| committer | Mahmoud Khairy A. Abdallah <[email protected]> | 2021-05-19 17:56:14 -0400 |
| commit | 14f22bcdd171cdeb8d8f56f9ed02d6f711189be8 (patch) | |
| tree | 4c5fea26b7bc4f6ec2428d620b5c098ed11bd520 /src | |
| parent | 6121a88e7f912c26736443038a940aee80967f59 (diff) | |
add checking on spec unit in subcore
Diffstat (limited to 'src')
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 6229d16..2513dde 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -108,7 +108,7 @@ void shader_core_ctx::create_front_pipeline() { if (m_config->sub_core_model) { // in subcore model, each scheduler should has its own issue register, so - // num scheduler = reg width + // ensure num scheduler = reg width assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_SP].get_size()); assert(m_config->gpgpu_num_sched_per_core == @@ -124,6 +124,11 @@ void shader_core_ctx::create_front_pipeline() { if (m_config->gpgpu_num_int_units > 0) assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_INT].get_size()); + for (int j = 0; j < m_config->m_specialized_unit.size(); j++) { + if (m_config->m_specialized_unit[j].num_units > 0) + assert(m_config->gpgpu_num_sched_per_core == + m_config->m_specialized_unit[j].id_oc_spec_reg_width); + } } m_threadState = (thread_ctx_t *)calloc(sizeof(thread_ctx_t), |