Fixing bug in printing - Not checking if cache was instantiated (i.e., L1D for Quadro config).

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16457]

2 files changed, 97 insertions, 84 deletions

diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 33393ee..dcbdfe0 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -909,32 +909,35 @@ void gpgpu_sim::gpu_print_stat()
       m_memory_partition_unit[i]->print(stdout);
 
    // L2 cache stats
-   cache_stats l2_stats;
-   struct cache_sub_stats l2_css;
-   struct cache_sub_stats total_l2_css;
-   l2_stats.clear();
-   l2_css.clear();
-   total_l2_css.clear();
+   if(!m_memory_config->m_L2_config.disabled()){
+       cache_stats l2_stats;
+       struct cache_sub_stats l2_css;
+       struct cache_sub_stats total_l2_css;
+       l2_stats.clear();
+       l2_css.clear();
+       total_l2_css.clear();
 
-   printf("\n========= L2 cache stats =========\n");
-   for (unsigned i=0;i<m_memory_config->m_n_mem;i++){
-       m_memory_partition_unit[i]->accumulate_L2cache_stats(l2_stats);
-       m_memory_partition_unit[i]->get_L2cache_sub_stats(l2_css);
+       printf("\n========= L2 cache stats =========\n");
+       for (unsigned i=0;i<m_memory_config->m_n_mem;i++){
+           m_memory_partition_unit[i]->accumulate_L2cache_stats(l2_stats);
+           m_memory_partition_unit[i]->get_L2cache_sub_stats(l2_css);
 
-       fprintf( stdout, "L2_cache_bank[%d]: Access = %u, Miss = %u, Miss_rate = %.3lf, Pending_hits = %u, Reservation_fails = %u\n",
-                i, l2_css.accesses, l2_css.misses, (double)l2_css.misses / (double)l2_css.accesses, l2_css.pending_hits, l2_css.res_fails);
+           fprintf( stdout, "L2_cache_bank[%d]: Access = %u, Miss = %u, Miss_rate = %.3lf, Pending_hits = %u, Reservation_fails = %u\n",
+                    i, l2_css.accesses, l2_css.misses, (double)l2_css.misses / (double)l2_css.accesses, l2_css.pending_hits, l2_css.res_fails);
 
-       total_l2_css += l2_css;
-   }
-   if (!m_memory_config->m_L2_config.disabled() && m_memory_config->m_L2_config.get_num_lines()) {
-      //L2c_print_cache_stat();
-      printf("L2_total_cache_accesses = %u\n", total_l2_css.accesses);
-      printf("L2_total_cache_misses = %u\n", total_l2_css.misses);
-      printf("L2_total_cache_miss_rate = %.4lf\n", (double)total_l2_css.misses/(double)total_l2_css.accesses);
-      printf("L2_total_cache_pending_hits = %u\n", total_l2_css.pending_hits);
-      printf("L2_total_cache_reservation_fails = %u\n", total_l2_css.res_fails);
-      printf("L2_total_cache_breakdown:\n");
-      l2_stats.print_stats(stdout, "L2_cache_stats_breakdown");
+           total_l2_css += l2_css;
+       }
+       if (!m_memory_config->m_L2_config.disabled() && m_memory_config->m_L2_config.get_num_lines()) {
+          //L2c_print_cache_stat();
+          printf("L2_total_cache_accesses = %u\n", total_l2_css.accesses);
+          printf("L2_total_cache_misses = %u\n", total_l2_css.misses);
+          if(total_l2_css.accesses > 0)
+              printf("L2_total_cache_miss_rate = %.4lf\n", (double)total_l2_css.misses/(double)total_l2_css.accesses);
+          printf("L2_total_cache_pending_hits = %u\n", total_l2_css.pending_hits);
+          printf("L2_total_cache_reservation_fails = %u\n", total_l2_css.res_fails);
+          printf("L2_total_cache_breakdown:\n");
+          l2_stats.print_stats(stdout, "L2_cache_stats_breakdown");
+       }
    }
 
    if (m_config.gpgpu_cflog_interval != 0) {
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index e108963..ba79721 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1110,13 +1110,16 @@ void ldst_unit::get_cache_stats(cache_stats &cs) {
 }
 
 void ldst_unit::get_L1D_sub_stats(struct cache_sub_stats &css) const{
-    m_L1D->get_sub_stats(css);
+    if(m_L1D)
+        m_L1D->get_sub_stats(css);
 }
 void ldst_unit::get_L1C_sub_stats(struct cache_sub_stats &css) const{
-    m_L1C->get_sub_stats(css);
+    if(m_L1C)
+        m_L1C->get_sub_stats(css);
 }
 void ldst_unit::get_L1T_sub_stats(struct cache_sub_stats &css) const{
-    m_L1T->get_sub_stats(css);
+    if(m_L1T)
+        m_L1T->get_sub_stats(css);
 }
 
 void shader_core_ctx::warp_inst_complete(const warp_inst_t &inst)
@@ -1878,75 +1881,81 @@ void gpgpu_sim::shader_print_cache_stats( FILE *fout ) const{
     struct cache_sub_stats total_css;
     struct cache_sub_stats css;
 
-    total_css.clear();
-    css.clear();
-
-    fprintf(fout, "\n========= Core cache stats =========\n");
-    fprintf(fout, "L1I_cache:\n");
-    for ( unsigned i = 0; i < m_shader_config->n_simt_clusters; ++i ) {
-        m_cluster[i]->get_L1I_sub_stats(css);
-        total_css += css;
-    }
-    fprintf(fout, "\tL1I_total_cache_accesses: %u\n", total_css.accesses);
-    fprintf(fout, "\tL1I_total_cache_misses: %u\n", total_css.misses);
-    if(total_css.accesses > 0){
-        fprintf(fout, "\tL1I_total_cache_miss_rate: %.4lf\n", (double)total_css.misses / (double)total_css.accesses);
+    if(!m_shader_config->m_L1I_config.disabled()){
+        total_css.clear();
+        css.clear();
+        fprintf(fout, "\n========= Core cache stats =========\n");
+        fprintf(fout, "L1I_cache:\n");
+        for ( unsigned i = 0; i < m_shader_config->n_simt_clusters; ++i ) {
+            m_cluster[i]->get_L1I_sub_stats(css);
+            total_css += css;
+        }
+        fprintf(fout, "\tL1I_total_cache_accesses: %u\n", total_css.accesses);
+        fprintf(fout, "\tL1I_total_cache_misses: %u\n", total_css.misses);
+        if(total_css.accesses > 0){
+            fprintf(fout, "\tL1I_total_cache_miss_rate: %.4lf\n", (double)total_css.misses / (double)total_css.accesses);
+        }
+        fprintf(fout, "\tL1I_total_cache_pending_hits: %u\n", total_css.pending_hits);
+        fprintf(fout, "\tL1I_total_cache_reservation_fails: %u\n", total_css.res_fails);
     }
-    fprintf(fout, "\tL1I_total_cache_pending_hits: %u\n", total_css.pending_hits);
-    fprintf(fout, "\tL1I_total_cache_reservation_fails: %u\n", total_css.res_fails);
 
     // L1D
-    total_css.clear();
-    css.clear();
-    fprintf(fout, "L1D_cache:\n");
-    for (unsigned i=0;i<m_shader_config->n_simt_clusters;i++){
-        m_cluster[i]->get_L1D_sub_stats(css);
+    if(!m_shader_config->m_L1D_config.disabled()){
+        total_css.clear();
+        css.clear();
+        fprintf(fout, "L1D_cache:\n");
+        for (unsigned i=0;i<m_shader_config->n_simt_clusters;i++){
+            m_cluster[i]->get_L1D_sub_stats(css);
 
-        fprintf( stdout, "\tL1D_cache_core[%d]: Access = %d, Miss = %d, Miss_rate = %.3lf, Pending_hits = %u, Reservation_fails = %u\n",
-                 i, css.accesses, css.misses, (double)css.misses / (double)css.accesses, css.pending_hits, css.res_fails);
+            fprintf( stdout, "\tL1D_cache_core[%d]: Access = %d, Miss = %d, Miss_rate = %.3lf, Pending_hits = %u, Reservation_fails = %u\n",
+                     i, css.accesses, css.misses, (double)css.misses / (double)css.accesses, css.pending_hits, css.res_fails);
 
-        total_css += css;
-    }
-    fprintf(fout, "\tL1D_total_cache_accesses: %u\n", total_css.accesses);
-    fprintf(fout, "\tL1D_total_cache_misses: %u\n", total_css.misses);
-    if(total_css.accesses > 0){
-        fprintf(fout, "\tL1D_total_cache_miss_rate: %.4lf\n", (double)total_css.misses / (double)total_css.accesses);
+            total_css += css;
+        }
+        fprintf(fout, "\tL1D_total_cache_accesses: %u\n", total_css.accesses);
+        fprintf(fout, "\tL1D_total_cache_misses: %u\n", total_css.misses);
+        if(total_css.accesses > 0){
+            fprintf(fout, "\tL1D_total_cache_miss_rate: %.4lf\n", (double)total_css.misses / (double)total_css.accesses);
+        }
+        fprintf(fout, "\tL1D_total_cache_pending_hits: %u\n", total_css.pending_hits);
+        fprintf(fout, "\tL1D_total_cache_reservation_fails: %u\n", total_css.res_fails);
     }
-    fprintf(fout, "\tL1D_total_cache_pending_hits: %u\n", total_css.pending_hits);
-    fprintf(fout, "\tL1D_total_cache_reservation_fails: %u\n", total_css.res_fails);
-
 
     // L1C
-    total_css.clear();
-    css.clear();
-    fprintf(fout, "L1C_cache:\n");
-    for ( unsigned i = 0; i < m_shader_config->n_simt_clusters; ++i ) {
-        m_cluster[i]->get_L1C_sub_stats(css);
-        total_css += css;
-    }
-    fprintf(fout, "\tL1C_total_cache_accesses: %u\n", total_css.accesses);
-    fprintf(fout, "\tL1C_total_cache_misses: %u\n", total_css.misses);
-    if(total_css.accesses > 0){
-        fprintf(fout, "\tL1C_total_cache_miss_rate: %.4lf\n", (double)total_css.misses / (double)total_css.accesses);
+    if(!m_shader_config->m_L1C_config.disabled()){
+        total_css.clear();
+        css.clear();
+        fprintf(fout, "L1C_cache:\n");
+        for ( unsigned i = 0; i < m_shader_config->n_simt_clusters; ++i ) {
+            m_cluster[i]->get_L1C_sub_stats(css);
+            total_css += css;
+        }
+        fprintf(fout, "\tL1C_total_cache_accesses: %u\n", total_css.accesses);
+        fprintf(fout, "\tL1C_total_cache_misses: %u\n", total_css.misses);
+        if(total_css.accesses > 0){
+            fprintf(fout, "\tL1C_total_cache_miss_rate: %.4lf\n", (double)total_css.misses / (double)total_css.accesses);
+        }
+        fprintf(fout, "\tL1C_total_cache_pending_hits: %u\n", total_css.pending_hits);
+        fprintf(fout, "\tL1C_total_cache_reservation_fails: %u\n", total_css.res_fails);
     }
-    fprintf(fout, "\tL1C_total_cache_pending_hits: %u\n", total_css.pending_hits);
-    fprintf(fout, "\tL1C_total_cache_reservation_fails: %u\n", total_css.res_fails);
 
     // L1T
-    total_css.clear();
-    css.clear();
-    fprintf(fout, "L1T_cache:\n");
-    for ( unsigned i = 0; i < m_shader_config->n_simt_clusters; ++i ) {
-        m_cluster[i]->get_L1T_sub_stats(css);
-        total_css += css;
-    }
-    fprintf(fout, "\tL1T_total_cache_accesses: %u\n", total_css.accesses);
-    fprintf(fout, "\tL1T_total_cache_misses: %u\n", total_css.misses);
-    if(total_css.accesses > 0){
-        fprintf(fout, "\tL1T_total_cache_miss_rate: %.4lf\n", (double)total_css.misses / (double)total_css.accesses);
+    if(!m_shader_config->m_L1T_config.disabled()){
+        total_css.clear();
+        css.clear();
+        fprintf(fout, "L1T_cache:\n");
+        for ( unsigned i = 0; i < m_shader_config->n_simt_clusters; ++i ) {
+            m_cluster[i]->get_L1T_sub_stats(css);
+            total_css += css;
+        }
+        fprintf(fout, "\tL1T_total_cache_accesses: %u\n", total_css.accesses);
+        fprintf(fout, "\tL1T_total_cache_misses: %u\n", total_css.misses);
+        if(total_css.accesses > 0){
+            fprintf(fout, "\tL1T_total_cache_miss_rate: %.4lf\n", (double)total_css.misses / (double)total_css.accesses);
+        }
+        fprintf(fout, "\tL1T_total_cache_pending_hits: %u\n", total_css.pending_hits);
+        fprintf(fout, "\tL1T_total_cache_reservation_fails: %u\n", total_css.res_fails);
     }
-    fprintf(fout, "\tL1T_total_cache_pending_hits: %u\n", total_css.pending_hits);
-    fprintf(fout, "\tL1T_total_cache_reservation_fails: %u\n", total_css.res_fails);
 }
 
 void gpgpu_sim::shader_print_l1_miss_stat( FILE *fout ) const
@@ -2613,7 +2622,8 @@ void shader_core_ctx::get_cache_stats(cache_stats &cs){
 }
 
 void shader_core_ctx::get_L1I_sub_stats(struct cache_sub_stats &css) const{
-    m_L1I->get_sub_stats(css);
+    if(m_L1I)
+        m_L1I->get_sub_stats(css);
 }
 void shader_core_ctx::get_L1D_sub_stats(struct cache_sub_stats &css) const{
     m_ldst_unit->get_L1D_sub_stats(css);