Move s_g_pc_to_insn

Signed-off-by: Mengchi Zhang <[email protected]>

12 files changed, 73 insertions, 73 deletions

diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index 733d602..d8d5fbd 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -426,7 +426,7 @@ void warp_inst_t::generate_mem_accesses()
         }
         assert( total_accesses > 0 && total_accesses <= m_config->warp_size );
         cycles = total_accesses; // shared memory conflicts modeled as larger initiation interval 
-        ptx_file_line_stats_add_smem_bank_conflict( pc, total_accesses );
+        m_config->gpgpu_ctx->stats->ptx_file_line_stats_add_smem_bank_conflict( pc, total_accesses );
         break;
     }
 
@@ -471,7 +471,7 @@ void warp_inst_t::generate_mem_accesses()
     }
 
     if ( space.get_type() == global_space ) {
-        ptx_file_line_stats_add_uncoalesced_gmem( pc, m_accessq.size() - starting_queue_size );
+        m_config->gpgpu_ctx->stats->ptx_file_line_stats_add_uncoalesced_gmem( pc, m_accessq.size() - starting_queue_size );
     }
     m_mem_accesses_created=true;
 }
@@ -706,7 +706,7 @@ void warp_inst_t::completed( unsigned long long cycle ) const
 {
    unsigned long long latency = cycle - issue_cycle; 
    assert(latency <= cycle); // underflow detection 
-   ptx_file_line_stats_add_latency(pc, latency * active_count());  
+   m_config->gpgpu_ctx->stats->ptx_file_line_stats_add_latency(pc, latency * active_count());  
 }
 
 
@@ -1110,7 +1110,7 @@ void simt_stack::update( simt_mask_t &thread_done, addr_vector_t &next_pc, addre
 
 
     if (warp_diverged) {
-        ptx_file_line_stats_add_warp_divergence(top_pc, 1); 
+        m_gpu->gpgpu_ctx->stats->ptx_file_line_stats_add_warp_divergence(top_pc, 1); 
     }
 }
 
@@ -1157,7 +1157,7 @@ warp_inst_t core_t::getExecuteWarp(unsigned warpId)
 {
     unsigned pc,rpc;
     m_simt_stack[warpId]->get_pdom_stack_top_info(&pc,&rpc);
-    warp_inst_t wi= *ptx_fetch_inst(pc);
+    warp_inst_t wi= *(m_gpu->gpgpu_ctx->ptx_fetch_inst(pc));
     wi.set_active(m_simt_stack[warpId]->get_active_mask());
     return wi;
 }
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index c06f093..b9e6552 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -215,8 +215,6 @@ void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref)
    m_NameToTextureInfo.erase(texname);
 }
 
-std::vector<ptx_instruction*> function_info::s_g_pc_to_insn;
-
 #define MAX_INST_SIZE 8 /*bytes*/
 
 void function_info::ptx_assemble()
@@ -237,14 +235,14 @@ void function_info::ptx_assemble()
    addr_t PC = gpgpu_ctx->func_sim->g_assemble_code_next_pc; // globally unique address (across functions)
    // start function on an aligned address
    for( unsigned i=0; i < (PC%MAX_INST_SIZE); i++ ) 
-      s_g_pc_to_insn.push_back((ptx_instruction*)NULL);
+      gpgpu_ctx->s_g_pc_to_insn.push_back((ptx_instruction*)NULL);
    PC += PC%MAX_INST_SIZE; 
    m_start_PC = PC;
 
    addr_t n=0; // offset in m_instr_mem
    //Why s_g_pc_to_insn.size() is needed to reserve additional memory for insts? reserve is cumulative.
    //s_g_pc_to_insn.reserve(s_g_pc_to_insn.size() + MAX_INST_SIZE*m_instructions.size());
-   s_g_pc_to_insn.reserve(MAX_INST_SIZE*m_instructions.size());
+   gpgpu_ctx->s_g_pc_to_insn.reserve(MAX_INST_SIZE*m_instructions.size());
    for ( i=m_instructions.begin(); i != m_instructions.end(); i++ ) {
       ptx_instruction *pI = *i;
       if ( pI->is_label() ) {
@@ -253,13 +251,13 @@ void function_info::ptx_assemble()
       } else {
          gpgpu_ctx->func_sim->g_pc_to_finfo[PC] = this;
          m_instr_mem[n] = pI;
-         s_g_pc_to_insn.push_back(pI);
-         assert(pI == s_g_pc_to_insn[PC]);
+         gpgpu_ctx->s_g_pc_to_insn.push_back(pI);
+         assert(pI == gpgpu_ctx->s_g_pc_to_insn[PC]);
          pI->set_m_instr_mem_index(n);
          pI->set_PC(PC);
          assert( pI->inst_size() <= MAX_INST_SIZE );
          for( unsigned i=1; i < pI->inst_size(); i++ ) {
-            s_g_pc_to_insn.push_back((ptx_instruction*)NULL);
+            gpgpu_ctx->s_g_pc_to_insn.push_back((ptx_instruction*)NULL);
             m_instr_mem[n+i]=NULL;
          }
          n  += pI->inst_size();
@@ -1738,9 +1736,9 @@ const struct gpgpu_ptx_sim_info* ptx_sim_kernel_info(const function_info *kernel
    return kernel->get_kernel_info();
 }
 
-const warp_inst_t *ptx_fetch_inst( address_type pc )
+const warp_inst_t *gpgpu_context::ptx_fetch_inst( address_type pc )
 {
-    return function_info::pc_to_instruction(pc);
+    return pc_to_instruction(pc);
 }
 
 unsigned ptx_sim_init_thread( kernel_info_t &kernel,
@@ -2366,11 +2364,11 @@ void functionalCoreSim::executeWarp(unsigned i, bool &allAtBarrier, bool & someO
     if(!m_warpAtBarrier[i]&& m_liveThreadCount[i]>0) allAtBarrier = false;
 }
 
-unsigned translate_pc_to_ptxlineno(unsigned pc)
+unsigned gpgpu_context::translate_pc_to_ptxlineno(unsigned pc)
 {
    // this function assumes that the kernel fits inside a single PTX file
    // function_info *pFunc = g_func_info; // assume that the current kernel is the one in query
-   const ptx_instruction *pInsn = function_info::pc_to_instruction(pc);
+   const ptx_instruction *pInsn = pc_to_instruction(pc);
    unsigned ptx_line_number = pInsn->source_line();
 
    return ptx_line_number;
diff --git a/src/cuda-sim/cuda-sim.h b/src/cuda-sim/cuda-sim.h
index 5bd4cb2..1be3d19 100644
--- a/src/cuda-sim/cuda-sim.h
+++ b/src/cuda-sim/cuda-sim.h
@@ -58,10 +58,8 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel,
                               unsigned hw_warp_id,
                               gpgpu_t *gpu,
                               bool functionalSimulationMode = false);
-const warp_inst_t *ptx_fetch_inst( address_type pc );
 const struct gpgpu_ptx_sim_info* ptx_sim_kernel_info(const class function_info *kernel);
 
-
 /*!
  * This class functionally executes a kernel. It uses the basic data structures and procedures in core_t 
  */
diff --git a/src/cuda-sim/ptx-stats.cc b/src/cuda-sim/ptx-stats.cc
index 298729f..22517df 100644
--- a/src/cuda-sim/ptx-stats.cc
+++ b/src/cuda-sim/ptx-stats.cc
@@ -151,27 +151,27 @@ void ptx_file_line_stats_add_exec_count(const ptx_instruction *pInsn)
 
 // attribute pipeline latency to this ptx instruction (specified by the pc)
 // pipeline latency is the number of cycles a warp with this instruction spent in the pipeline
-void ptx_file_line_stats_add_latency(unsigned pc, unsigned latency)
+void ptx_stats::ptx_file_line_stats_add_latency(unsigned pc, unsigned latency)
 {
-    const ptx_instruction *pInsn = function_info::pc_to_instruction(pc);
+    const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
     
     ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())].latency += latency;
 }
 
 // attribute dram traffic to this ptx instruction (specified by the pc)
 // dram traffic is counted in number of requests 
-void ptx_file_line_stats_add_dram_traffic(unsigned pc, unsigned dram_traffic)
+void ptx_stats::ptx_file_line_stats_add_dram_traffic(unsigned pc, unsigned dram_traffic)
 {
-    const ptx_instruction *pInsn = function_info::pc_to_instruction(pc);
+    const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
     
     ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())].dram_traffic += dram_traffic;
 }
 
 // attribute the number of shared memory access cycles to a ptx instruction
 // counts both the number of warps doing shared memory access and the number of cycles involved
-void ptx_file_line_stats_add_smem_bank_conflict(unsigned pc, unsigned n_way_bkconflict)
+void ptx_stats::ptx_file_line_stats_add_smem_bank_conflict(unsigned pc, unsigned n_way_bkconflict)
 {
-    const ptx_instruction *pInsn = function_info::pc_to_instruction(pc);
+    const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
     
     ptx_file_line_stats& line_stats = ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())];
     line_stats.smem_n_way_bank_conflict_total += n_way_bkconflict;
@@ -180,9 +180,9 @@ void ptx_file_line_stats_add_smem_bank_conflict(unsigned pc, unsigned n_way_bkco
 
 // attribute a non-coalesced mem access to a ptx instruction 
 // counts both the number of warps causing this and the number of memory requests generated
-void ptx_file_line_stats_add_uncoalesced_gmem(unsigned pc, unsigned n_access)
+void ptx_stats::ptx_file_line_stats_add_uncoalesced_gmem(unsigned pc, unsigned n_access)
 {
-    const ptx_instruction *pInsn = function_info::pc_to_instruction(pc);
+    const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
     
     ptx_file_line_stats& line_stats = ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())];
     line_stats.gmem_n_access_total += n_access;
@@ -239,17 +239,17 @@ void ptx_file_line_stats_create_exposed_latency_tracker(int n_shader_cores)
 }
 
 // add an inflight memory instruction
-void ptx_file_line_stats_add_inflight_memory_insn(int sc_id, unsigned pc)
+void ptx_stats::ptx_file_line_stats_add_inflight_memory_insn(int sc_id, unsigned pc)
 {
-    const ptx_instruction *pInsn = function_info::pc_to_instruction(pc);
+    const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
 
     inflight_mem_tracker[sc_id].add_count(pInsn);
 }
 
 // remove an inflight memory instruction
-void ptx_file_line_stats_sub_inflight_memory_insn(int sc_id, unsigned pc)
+void ptx_stats::ptx_file_line_stats_sub_inflight_memory_insn(int sc_id, unsigned pc)
 {
-    const ptx_instruction *pInsn = function_info::pc_to_instruction(pc);
+    const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
 
     inflight_mem_tracker[sc_id].sub_count(pInsn);
 }
@@ -262,9 +262,9 @@ void ptx_file_line_stats_commit_exposed_latency(int sc_id, int exposed_latency)
 }
 
 // attribute the number of warp divergence to a ptx instruction
-void ptx_file_line_stats_add_warp_divergence(unsigned pc, unsigned n_way_divergence)
+void ptx_stats::ptx_file_line_stats_add_warp_divergence(unsigned pc, unsigned n_way_divergence)
 {
-    const ptx_instruction *pInsn = function_info::pc_to_instruction(pc);
+    const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
     
     ptx_file_line_stats& line_stats = ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())];
     line_stats.warp_divergence += n_way_divergence;
diff --git a/src/cuda-sim/ptx-stats.h b/src/cuda-sim/ptx-stats.h
index c75fc58..246b4ce 100644
--- a/src/cuda-sim/ptx-stats.h
+++ b/src/cuda-sim/ptx-stats.h
@@ -37,17 +37,10 @@ void ptx_file_line_stats_add_exec_count(const ptx_instruction *pInsn);
 #endif
 
 // stat collection interface to gpgpu-sim
-void ptx_file_line_stats_add_latency(unsigned pc, unsigned latency);
-void ptx_file_line_stats_add_dram_traffic(unsigned pc, unsigned dram_traffic);
-void ptx_file_line_stats_add_smem_bank_conflict(unsigned pc, unsigned n_way_bkconflict);
-void ptx_file_line_stats_add_uncoalesced_gmem(unsigned pc, unsigned n_access);
 
 void ptx_file_line_stats_create_exposed_latency_tracker(int n_shader_cores);
-void ptx_file_line_stats_add_inflight_memory_insn(int sc_id, unsigned pc);
-void ptx_file_line_stats_sub_inflight_memory_insn(int sc_id, unsigned pc);
 void ptx_file_line_stats_commit_exposed_latency(int sc_id, int exposed_latency);
 
-void ptx_file_line_stats_add_warp_divergence(unsigned pc, unsigned n_way_divergence);
 
 class gpgpu_context;
 class ptx_stats {
@@ -64,4 +57,12 @@ class ptx_stats {
 
 	// output stats to a file
 	void ptx_file_line_stats_write_file();
+	// stat collection interface to gpgpu-sim
+	void ptx_file_line_stats_add_latency(unsigned pc, unsigned latency);
+	void ptx_file_line_stats_add_dram_traffic(unsigned pc, unsigned dram_traffic);
+	void ptx_file_line_stats_add_smem_bank_conflict(unsigned pc, unsigned n_way_bkconflict);
+	void ptx_file_line_stats_add_uncoalesced_gmem(unsigned pc, unsigned n_access);
+	void ptx_file_line_stats_add_inflight_memory_insn(int sc_id, unsigned pc);
+	void ptx_file_line_stats_sub_inflight_memory_insn(int sc_id, unsigned pc);
+	void ptx_file_line_stats_add_warp_divergence(unsigned pc, unsigned n_way_divergence);
 };
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index 5fa9379..3384d49 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -43,6 +43,14 @@ typedef void * yyscan_t;
 
 #define STR_SIZE 1024
 
+const ptx_instruction* gpgpu_context::pc_to_instruction(unsigned pc) 
+{
+    if( pc < s_g_pc_to_insn.size() )
+	return s_g_pc_to_insn[pc];
+    else
+	return NULL;
+}
+
 unsigned symbol::get_uid()
 {
    unsigned result = (gpgpu_ctx->symbol_sm_next_uid)++;
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index 8fc0a06..f4c5c37 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -1372,13 +1372,6 @@ public:
       return m_symtab;
    }
 
-   static const ptx_instruction* pc_to_instruction(unsigned pc) 
-   {
-      if( pc < s_g_pc_to_insn.size() )
-          return s_g_pc_to_insn[pc];
-      else
-          return NULL;
-   }
    unsigned local_mem_framesize() const 
    { 
       return m_local_mem_framesize; 
@@ -1436,8 +1429,6 @@ private:
 
    symbol_table *m_symtab;
 
-   static std::vector<ptx_instruction*> s_g_pc_to_insn; // a direct mapping from PC to instruction
-
    //parameter size for device kernels
    int m_args_aligned_size;
    
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index bdf989a..e4ae04f 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -886,7 +886,7 @@ void gpgpu_sim::init()
     m_shader_stats->new_grid();
     // initialize the control-flow, memory access, memory latency logger
     if (m_config.g_visualizer_enabled) {
-        create_thread_CFlogger( m_config.num_shader(), m_shader_config->n_thread_per_shader, 0, m_config.gpgpu_cflog_interval );
+        create_thread_CFlogger( gpgpu_ctx, m_config.num_shader(), m_shader_config->n_thread_per_shader, 0, m_config.gpgpu_cflog_interval );
     }
     shader_CTA_count_create( m_config.num_shader(), m_config.gpgpu_cflog_interval);
     if (m_config.gpgpu_cflog_interval != 0) {
diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc
index 4e94991..a1b43a8 100644
--- a/src/gpgpu-sim/mem_latency_stat.cc
+++ b/src/gpgpu-sim/mem_latency_stat.cc
@@ -41,6 +41,7 @@
 #include <string.h>
 #include <stdlib.h>
 #include <stdio.h>
+#include "../../libcuda/gpgpu_context.h"
 
 memory_stats_t::memory_stats_t( unsigned n_shader, const shader_core_config *shader_config, const memory_config *mem_config, const class gpgpu_sim* gpu )
 {
@@ -195,7 +196,7 @@ void memory_stats_t::memlatstat_dram_access(mem_fetch *mf)
       mem_access_type_stats[mf->get_access_type()][dram_id][bank]++;
    }
    if (mf->get_pc() != (unsigned)-1) 
-      ptx_file_line_stats_add_dram_traffic(mf->get_pc(), mf->get_data_size());
+      m_gpu->gpgpu_ctx->stats->ptx_file_line_stats_add_dram_traffic(mf->get_pc(), mf->get_data_size());
 }
 
 void memory_stats_t::memlatstat_icnt2mem_pop(mem_fetch *mf)
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index b7ae95d..c697450 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -744,7 +744,7 @@ void shader_core_ctx::decode()
     if( m_inst_fetch_buffer.m_valid ) {
         // decode 1 or 2 instructions and place them into ibuffer
         address_type pc = m_inst_fetch_buffer.m_pc;
-        const warp_inst_t* pI1 = ptx_fetch_inst(pc);
+        const warp_inst_t* pI1 = m_gpu->gpgpu_ctx->ptx_fetch_inst(pc);
         m_warp[m_inst_fetch_buffer.m_warp_id].ibuffer_fill(0,pI1);
         m_warp[m_inst_fetch_buffer.m_warp_id].inc_inst_in_pipeline();
         if( pI1 ) {
@@ -754,7 +754,7 @@ void shader_core_ctx::decode()
             }else if(pI1->oprnd_type==FP_OP) {
             	m_stats->m_num_FPdecoded_insn[m_sid]++;
             }
-           const warp_inst_t* pI2 = ptx_fetch_inst(pc+pI1->isize);
+           const warp_inst_t* pI2 = m_gpu->gpgpu_ctx->ptx_fetch_inst(pc+pI1->isize);
            if( pI2 ) {
                m_warp[m_inst_fetch_buffer.m_warp_id].ibuffer_fill(1,pI2);
                m_warp[m_inst_fetch_buffer.m_warp_id].inc_inst_in_pipeline();
diff --git a/src/gpgpu-sim/stat-tool.cc b/src/gpgpu-sim/stat-tool.cc
index 6a4c75b..35a4cc3 100644
--- a/src/gpgpu-sim/stat-tool.cc
+++ b/src/gpgpu-sim/stat-tool.cc
@@ -37,6 +37,7 @@
 #include <map>
 #include <algorithm>
 #include <string>
+#include "../../libcuda/gpgpu_context.h"
 
 ////////////////////////////////////////////////////////////////////////////////
 
@@ -110,12 +111,10 @@ void spill_log_to_file (FILE *fout, int final, unsigned long long  current_cycle
 
 ////////////////////////////////////////////////////////////////////////////////
 
-unsigned translate_pc_to_ptxlineno(unsigned pc);
-
 static int n_thread_CFloggers = 0;
 static thread_CFlocality** thread_CFlogger = NULL;
 
-void create_thread_CFlogger( int n_loggers, int n_threads, address_type start_pc, unsigned long long  logging_interval) 
+void create_thread_CFlogger(gpgpu_context* ctx, int n_loggers, int n_threads, address_type start_pc, unsigned long long  logging_interval) 
 {
    destroy_thread_CFlogger();
    
@@ -126,7 +125,7 @@ void create_thread_CFlogger( int n_loggers, int n_threads, address_type start_pc
    char buffer[32];
    for (int i = 0; i < n_thread_CFloggers; i++) {
       snprintf(buffer, 32, "%02d", i);
-      thread_CFlogger[i] = new thread_CFlocality( name_tpl + buffer, logging_interval, n_threads, start_pc);
+      thread_CFlogger[i] = new thread_CFlocality( ctx, name_tpl + buffer, logging_interval, n_threads, start_pc);
       if (logging_interval != 0) {
          add_snap_shot_trigger(thread_CFlogger[i]);
          add_spill_log(thread_CFlogger[i]);
@@ -368,10 +367,10 @@ static int s_cache_access_logger_n_types = 0;
 static std::vector<linear_histogram_logger> s_cache_access_logger;
 
 enum cache_access_logger_types {
-   NORMAL, TEXTURE, CONSTANT, INSTRUCTION
+   NORMALS, TEXTURE, CONSTANT, INSTRUCTION
 };
 
-int get_shader_normal_cache_id() { return NORMAL; }
+int get_shader_normal_cache_id() { return NORMALS; }
 int get_shader_texture_cache_id() { return TEXTURE; }
 int get_shader_constant_cache_id() { return CONSTANT; }
 int get_shader_instruction_cache_id() { return INSTRUCTION; }
@@ -394,7 +393,7 @@ void shader_cache_access_log( int logger_id, int type, int miss)
 {
    if (s_cache_access_logger_n_types == 0) return;
    if (logger_id < 0) return;
-   assert(type == NORMAL || type == TEXTURE || type == CONSTANT || type == INSTRUCTION);
+   assert(type == NORMALS || type == TEXTURE || type == CONSTANT || type == INSTRUCTION);
    assert(miss == 0 || miss == 1);
    
    s_cache_access_logger[logger_id].log(2 * type + miss);
@@ -404,7 +403,7 @@ void shader_cache_access_unlog( int logger_id, int type, int miss)
 {
    if (s_cache_access_logger_n_types == 0) return;
    if (logger_id < 0) return;
-   assert(type == NORMAL || type == TEXTURE || type == CONSTANT || type == INSTRUCTION);
+   assert(type == NORMALS || type == TEXTURE || type == CONSTANT || type == INSTRUCTION);
    assert(miss == 0 || miss == 1);
    
    s_cache_access_logger[logger_id].unlog(2 * type + miss);
@@ -477,22 +476,24 @@ void shader_CTA_count_visualizer_gzprint( gzFile fout )
 ////////////////////////////////////////////////////////////////////////////////
 ////////////////////////////////////////////////////////////////////////////////
 
-thread_insn_span::thread_insn_span(unsigned long long  cycle)
+thread_insn_span::thread_insn_span(unsigned long long  cycle, gpgpu_context* ctx)
   : m_cycle(cycle),
 #if (tr1_hash_map_ismap == 1)
      m_insn_span_count() 
 #else 
      m_insn_span_count(32*1024) 
 #endif
-{ 
+{
+    gpgpu_ctx = ctx;
 }
 
 thread_insn_span::~thread_insn_span() { }
    
-thread_insn_span::thread_insn_span(const thread_insn_span& other)
+thread_insn_span::thread_insn_span(const thread_insn_span& other, gpgpu_context* ctx)
       : m_cycle(other.m_cycle),
-        m_insn_span_count(other.m_insn_span_count) 
+        m_insn_span_count(other.m_insn_span_count)
 { 
+    gpgpu_ctx = ctx;
 }
       
 thread_insn_span& thread_insn_span::operator=(const thread_insn_span& other)
@@ -551,7 +552,7 @@ void thread_insn_span::print_sparse_histo(FILE *fout) const
    int n_printed_entries = 0;
    span_count_map::const_iterator i_sc = m_insn_span_count.begin();
    for (; i_sc != m_insn_span_count.end(); ++i_sc) {
-      unsigned ptx_lineno = translate_pc_to_ptxlineno(i_sc->first);
+      unsigned ptx_lineno = gpgpu_ctx->translate_pc_to_ptxlineno(i_sc->first);
       fprintf(fout, "%u %d ", ptx_lineno, i_sc->second);
       n_printed_entries++;
    }
@@ -566,7 +567,7 @@ void thread_insn_span::print_sparse_histo(gzFile fout) const
    int n_printed_entries = 0;
    span_count_map::const_iterator i_sc = m_insn_span_count.begin();
    for (; i_sc != m_insn_span_count.end(); ++i_sc) {
-      unsigned ptx_lineno = translate_pc_to_ptxlineno(i_sc->first);
+      unsigned ptx_lineno = gpgpu_ctx->translate_pc_to_ptxlineno(i_sc->first);
       gzprintf(fout, "%u %d ", ptx_lineno, i_sc->second);
       n_printed_entries++;
    }
@@ -578,14 +579,14 @@ void thread_insn_span::print_sparse_histo(gzFile fout) const
 
 ////////////////////////////////////////////////////////////////////////////////
 
-thread_CFlocality::thread_CFlocality(std::string name, 
+thread_CFlocality::thread_CFlocality( gpgpu_context* ctx, std::string name, 
                                      unsigned long long  snap_shot_interval, 
                                      int nthreads, 
                                      address_type start_pc, 
                                      unsigned long long  start_cycle)
       : snap_shot_trigger(snap_shot_interval), m_name(name),
         m_nthreads(nthreads), m_thread_pc(nthreads, start_pc), m_cycle(start_cycle),
-        m_thd_span(start_cycle)
+        m_thd_span(start_cycle, ctx)
 {
    std::fill(m_thread_pc.begin(), m_thread_pc.end(), -1); // so that hw thread with no work assigned will not clobber results
 }
diff --git a/src/gpgpu-sim/stat-tool.h b/src/gpgpu-sim/stat-tool.h
index 5646f01..67b3923 100644
--- a/src/gpgpu-sim/stat-tool.h
+++ b/src/gpgpu-sim/stat-tool.h
@@ -35,6 +35,7 @@
 #include <stdio.h>
 #include <zlib.h>
 
+class gpgpu_context;
 /////////////////////////////////////////////////////////////////////////////////////
 // logger snapshot trigger: 
 // - automate the snap_shot part of loggers to avoid modifying simulation loop everytime 
@@ -80,8 +81,8 @@ public:
 
 class thread_insn_span {
 public:
-   thread_insn_span(unsigned long long  cycle);
-   thread_insn_span(const thread_insn_span& other);
+   thread_insn_span(unsigned long long  cycle, gpgpu_context* ctx);
+   thread_insn_span(const thread_insn_span& other, gpgpu_context* ctx);
    ~thread_insn_span();
    
    thread_insn_span& operator=(const thread_insn_span& other);
@@ -94,7 +95,8 @@ public:
    void print_sparse_histo(FILE *fout) const;
    void print_sparse_histo(gzFile fout) const;
 
-private: 
+private:
+   gpgpu_context* gpgpu_ctx;
    typedef tr1_hash_map<address_type, int> span_count_map;
    unsigned long long  m_cycle;
    span_count_map m_insn_span_count;
@@ -102,7 +104,7 @@ private:
 
 class thread_CFlocality : public snap_shot_trigger, public spill_log_interface {
 public:
-   thread_CFlocality(std::string name, unsigned long long  snap_shot_interval, 
+   thread_CFlocality(gpgpu_context* ctx, std::string name, unsigned long long  snap_shot_interval, 
                      int nthreads, address_type start_pc, unsigned long long  start_cycle = 0);
    ~thread_CFlocality();
    
@@ -270,7 +272,7 @@ void try_snap_shot (unsigned long long  current_cycle);
 void set_spill_interval (unsigned long long  interval);
 void spill_log_to_file (FILE *fout, int final, unsigned long long  current_cycle);
 
-void create_thread_CFlogger( int n_loggers, int n_threads, address_type start_pc, unsigned long long  logging_interval);
+void create_thread_CFlogger(gpgpu_context* ctx,  int n_loggers, int n_threads, address_type start_pc, unsigned long long  logging_interval);
 void destroy_thread_CFlogger( );
 void cflog_update_thread_pc( int logger_id, int thread_id, address_type pc );
 void cflog_snapshot( int logger_id, unsigned long long  cycle );