- add '-keep' option to keep intermediate files (used for OpenCL only right now)

- remove redundant initialization code of options (which confuses new users)
- make bool option variables bool type
- remove some more extern decls

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7247]

23 files changed, 178 insertions, 122 deletions

diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 9d62a59..c471a5c 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -83,7 +83,7 @@
 #include "ptx_sim.h"
 #include "../gpgpusim_entrypoint.h"
 
-int gpgpu_ptx_instruction_classification=0;
+int gpgpu_ptx_instruction_classification;
 void ** g_inst_classification_stat = NULL;
 void ** g_inst_op_classification_stat= NULL;
 int g_ptx_kernel_count = -1; // used for classification stat collection purposes 
@@ -1327,7 +1327,7 @@ void gpgpu_ptx_sim_memcpy_symbol(const char *hostVar, const void *src, size_t co
    fflush(stdout);
 }
 
-int g_ptx_sim_mode=0; // if non-zero run functional simulation only (i.e., no notion of a clock cycle)
+int g_ptx_sim_mode; // if non-zero run functional simulation only (i.e., no notion of a clock cycle)
 
 extern "C" int ptx_debug;
 
diff --git a/src/cuda-sim/cuda_device_printf.cc b/src/cuda-sim/cuda_device_printf.cc
index 197a5dd..9edeb5e 100644
--- a/src/cuda-sim/cuda_device_printf.cc
+++ b/src/cuda-sim/cuda_device_printf.cc
@@ -62,6 +62,7 @@
  * Vancouver, BC V6T 1Z4
  */
 
+#include "cuda_device_printf.h"
 #include "ptx_ir.h"
 
 void decode_space( memory_space_t &space, const ptx_thread_info *thread, const operand_info &op, memory_space *&mem, addr_t &addr);
diff --git a/src/cuda-sim/cuda_device_printf.h b/src/cuda-sim/cuda_device_printf.h
new file mode 100644
index 0000000..022b555
--- /dev/null
+++ b/src/cuda-sim/cuda_device_printf.h
@@ -0,0 +1,70 @@
+/* 
+ * Copyright (c) 2009 by Tor M. Aamodt, Ali Bakhoda, Joey Ting, Dan O'Connor, 
+ * Clive Lin, George L. Yuan, Wilson W. L. Fung and the 
+ * University of British Columbia
+ * Vancouver, BC  V6T 1Z4
+ * All Rights Reserved.
+ * 
+ * THIS IS A LEGAL DOCUMENT BY DOWNLOADING GPGPU-SIM, YOU ARE AGREEING TO THESE
+ * TERMS AND CONDITIONS.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * NOTE: The files libcuda/cuda_runtime_api.c and src/cuda-sim/cuda-math.h
+ * are derived from the CUDA Toolset available from http://www.nvidia.com/cuda
+ * (property of NVIDIA).  The files benchmarks/BlackScholes/ and 
+ * benchmarks/template/ are derived from the CUDA SDK available from 
+ * http://www.nvidia.com/cuda (also property of NVIDIA).  The files from 
+ * src/intersim/ are derived from Booksim (a simulator provided with the 
+ * textbook "Principles and Practices of Interconnection Networks" available 
+ * from http://cva.stanford.edu/books/ppin/). As such, those files are bound by 
+ * the corresponding legal terms and conditions set forth separately (original 
+ * copyright notices are left in files from these sources and where we have 
+ * modified a file our copyright notice appears before the original copyright 
+ * notice).  
+ * 
+ * Using this version of GPGPU-Sim requires a complete installation of CUDA 
+ * which is distributed seperately by NVIDIA under separate terms and 
+ * conditions.  To use this version of GPGPU-Sim with OpenCL requires a
+ * recent version of NVIDIA's drivers which support OpenCL.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 
+ * 3. Neither the name of the University of British Columbia nor the names of
+ * its contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ * 
+ * 4. This version of GPGPU-SIM is distributed freely for non-commercial use only.  
+ *  
+ * 5. No nonprofit user may place any restrictions on the use of this software,
+ * including as modified by the user, by any other authorized user.
+ * 
+ * 6. GPGPU-SIM was developed primarily by Tor M. Aamodt, Wilson W. L. Fung, 
+ * Ali Bakhoda, George L. Yuan, at the University of British Columbia, 
+ * Vancouver, BC V6T 1Z4
+ */
+
+#ifndef CUDA_DEVICE_PRINTF_INCLUDED
+#define CUDA_DEVICE_PRINTF_INCLUDED
+
+void gpgpusim_cuda_vprintf(const class ptx_instruction * pI, const class ptx_thread_info * thread, const class function_info * target_func );
+
+#endif
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 0924eab..47b3ebb 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -75,6 +75,9 @@
 #include "cuda-math.h"
 #include "../abstract_hardware_model.h"
 #include "ptx_loader.h"
+#include "cuda_device_printf.h"
+#include "../gpgpu-sim/gpu-sim.h"
+#include "../gpgpu-sim/shader.h"
 
 #include <stdarg.h>
 
@@ -678,11 +681,6 @@ void bra_impl( const ptx_instruction *pI, ptx_thread_info *thread )
 void brev_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); }
 void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); }
 
-extern int gpgpu_simd_model;
-#define POST_DOMINATOR 1 /* must match enum value in shader.h */
-void get_pdom_stack_top_info( unsigned sid, unsigned tid, unsigned *npc, unsigned *rpc );
-void gpgpusim_cuda_vprintf(const ptx_instruction * pI, const ptx_thread_info * thread, const function_info * target_func ); 
-
 void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
 {
    static unsigned call_uid_next = 1;
diff --git a/src/cuda-sim/ptx-stats.cc b/src/cuda-sim/ptx-stats.cc
index 6e7e6ec..df95960 100644
--- a/src/cuda-sim/ptx-stats.cc
+++ b/src/cuda-sim/ptx-stats.cc
@@ -71,7 +71,7 @@
 extern function_info *g_func_info;
 
 // options
-int enable_ptx_file_line_stats;
+bool enable_ptx_file_line_stats;
 char * ptx_line_stats_filename = NULL;
 
 void ptx_file_line_stats_options(option_parser_t opp)
diff --git a/src/cuda-sim/ptx-stats.h b/src/cuda-sim/ptx-stats.h
index 200f7a5..004433b 100644
--- a/src/cuda-sim/ptx-stats.h
+++ b/src/cuda-sim/ptx-stats.h
@@ -63,7 +63,7 @@
 
 #include "../option_parser.h"
 
-extern int enable_ptx_file_line_stats;
+extern bool enable_ptx_file_line_stats;
 
 // set options
 void ptx_file_line_stats_options(option_parser_t opp);
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index ce68505..3a2a4e3 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -1272,6 +1272,8 @@ extern std::map<std::string,symbol_table*> g_sym_name_to_symbol_table;
 
 #define STATIC_ALLOC_LIMIT (GLOBAL_HEAP_START - (TOTAL_LOCAL_MEM+TOTAL_SHARED_MEM))
 
+extern bool g_keep_intermediate_files;
+
 void gpgpu_ptx_assemble( std::string kname, void *kinfo );
 #include "../option_parser.h"
 void ptx_reg_options(option_parser_t opp);
diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc
index 713bdb3..783ce91 100644
--- a/src/cuda-sim/ptx_loader.cc
+++ b/src/cuda-sim/ptx_loader.cc
@@ -299,13 +299,17 @@ void gpgpu_ptx_sim_add_ptxstring( const char *ptx_string, const char *sourcefnam
     }
 }
 
-static int g_save_embedded_ptx = 0;
+static bool g_save_embedded_ptx;
+bool g_keep_intermediate_files;
 
 void ptx_reg_options(option_parser_t opp)
 {
    option_parser_register(opp, "-save_embedded_ptx", OPT_BOOL, &g_save_embedded_ptx, 
                 "saves ptx files embedded in binary as <n>.ptx",
                 "0");
+   option_parser_register(opp, "-keep", OPT_BOOL, &g_keep_intermediate_files, 
+                "keep intermediate files created by GPGPU-Sim when interfacing with external programs",
+                "0");
 }
 
 void print_ptx_file( const char *p, unsigned source_num, const char *filename )
diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc
index 2156bd6..b433fb3 100644
--- a/src/cuda-sim/ptx_sim.cc
+++ b/src/cuda-sim/ptx_sim.cc
@@ -65,6 +65,7 @@
 #include <string>
 #include "ptx_ir.h"
 #include "../gpgpu-sim/gpu-sim.h"
+#include "../gpgpu-sim/shader.h"
 
 void feature_not_implemented( const char *f );
 
@@ -358,11 +359,6 @@ void ptx_thread_info::callstack_push( unsigned pc, unsigned rpc, const symbol *r
    m_local_mem_stack_pointer += m_func_info->local_mem_framesize(); 
 }
 
-#define POST_DOMINATOR 1 /* must match definition in shader.h */
-extern int gpgpu_simd_model;
-extern ptx_reg_t get_operand_value( const symbol *reg );
-extern void set_operand_value( const symbol *dst, const ptx_reg_t &data );
-
 bool ptx_thread_info::callstack_pop()
 {
    const symbol *rv_src = m_callstack.back().m_return_var_src;
diff --git a/src/debug.cc b/src/debug.cc
index 6bddb48..ac0daec 100644
--- a/src/debug.cc
+++ b/src/debug.cc
@@ -60,7 +60,7 @@ void gpgpu_debug()
       if( b.is_watchpoint() ) {
          unsigned addr = b.get_addr();
          unsigned new_value = read_location(addr);
-         if( new_value != b.get_value() ) {
+         if( new_value != b.get_value() || g_watchpoint_hits.find(num) != g_watchpoint_hits.end() ) {
             printf( "GPGPU-Sim PTX DBG: watch point %u triggered (old value=%x, new value=%x)\n",
                      num,b.get_value(),new_value );
             std::map<unsigned,watchpoint_event>::iterator w=g_watchpoint_hits.find(num);
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index 0ed44d0..f3a9091 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -190,7 +190,7 @@ unsigned int LOGB2_32( unsigned int v ) {
 }
 
 
-static char *addrdec_option = NULL;
+static char *addrdec_option;
 void addrdec_setoption(option_parser_t opp)
 {
    option_parser_register(opp, "-gpgpu_mem_addr_mapping", OPT_CSTR, &addrdec_option,
diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h
index cd92fa9..ee5fc77 100644
--- a/src/gpgpu-sim/dram.h
+++ b/src/gpgpu-sim/dram.h
@@ -79,13 +79,11 @@
 #define FIFO_NUM_WRITE_LIMIT 3   //used for both BANK_CONF and REALISTIC schedulers
 #define LOOKAHEAD_VALUE 10    //used for REALISTIC scheduler ONLY
 
-enum {
-   DRAM_FIFO,
-   DRAM_IDEAL_FAST,
-   DRAM_NUM_HANDLES
+enum dram_ctrl_t {
+   DRAM_FIFO=0,
+   DRAM_IDEAL_FAST=1
 };
 
-
 #define READ 'R'  //define read and write states
 #define WRITE 'W'
 typedef struct {
diff --git a/src/gpgpu-sim/dwf.cc b/src/gpgpu-sim/dwf.cc
index 0cad2b6..7c5305c 100644
--- a/src/gpgpu-sim/dwf.cc
+++ b/src/gpgpu-sim/dwf.cc
@@ -74,8 +74,8 @@
 
 using namespace std;
 
-unsigned int gpgpu_dwf_regbk = 1;
-unsigned int gpgpu_dwf_heuristic = 0;
+bool gpgpu_dwf_regbk;
+unsigned int gpgpu_dwf_heuristic;
 enum {
    MAJORITY  = 0,
    MINORITY  = 1,
@@ -2322,8 +2322,6 @@ void g_print_max_heap(int sid) {
    #undef UNIT_TEST
    #include "stat-tool.cc"
 
-unsigned gpgpu_thread_swizzling = 0;
-
 int regfile_hash(signed istream_number, unsigned simd_size, unsigned n_banks) {
    if (gpgpu_thread_swizzling) {
       signed warp_ID = istream_number / simd_size;
diff --git a/src/gpgpu-sim/dwf.h b/src/gpgpu-sim/dwf.h
index 75c06da..547abb4 100644
--- a/src/gpgpu-sim/dwf.h
+++ b/src/gpgpu-sim/dwf.h
@@ -116,6 +116,6 @@ void dwf_set_accPC( int n_shaders, unsigned *acc_pc_count );
 void dwf_update_statistics( int shader_id );
 
 extern unsigned int gpgpu_dwf_heuristic;
-extern unsigned int gpgpu_dwf_regbk;
+extern bool gpgpu_dwf_regbk;
 
 #endif
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index b716acc..e0549e1 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -152,39 +152,36 @@ char *gpgpu_runtime_stat;
 int gpu_stat_sample_freq = 10000;
 int gpu_runtime_stat_flag = 0;
 
-// GPGPU options
 unsigned long long  gpu_max_cycle = 0;
 unsigned long long  gpu_max_insn = 0;
-int gpu_max_cycle_opt = 0;
-int gpu_max_insn_opt = 0;
-int gpu_max_cta_opt = 0;
-int gpu_deadlock_detect = 0;
 int gpu_deadlock = 0;
+unsigned g_next_mf_request_uid = 1;
 static unsigned long long  last_gpu_sim_insn = 0;
-int gpgpu_dram_scheduler = DRAM_FIFO;
-int gpgpu_simd_model = 0;
-int gpgpu_no_dl1 = 0;
+int g_nthreads_issued;
+int g_total_cta_left;
+
+// GPGPU-Sim timing model options
+int   gpu_max_cycle_opt;
+int   gpu_max_insn_opt;
+int   gpu_max_cta_opt;
+bool  gpu_deadlock_detect;
+int   gpgpu_simd_model;
+enum dram_ctrl_t gpgpu_dram_scheduler;
+bool  gpgpu_no_dl1;
 char *gpgpu_cache_texl1_opt;
 char *gpgpu_cache_constl1_opt;
 char *gpgpu_cache_dl1_opt;
 char *gpgpu_cache_dl2_opt;
-int gpgpu_partial_write_mask = 0;
-
-bool gpgpu_perfect_mem = false;
+int   gpgpu_partial_write_mask;
+bool  gpgpu_perfect_mem;
 char *gpgpu_shader_core_pipeline_opt;
-unsigned int gpgpu_dram_buswidth = 4;
-unsigned int gpgpu_dram_burst_length = 4;
-int gpgpu_dram_sched_queue_size = 0; 
-char * gpgpu_dram_timing_opt;
-int gpgpu_flush_cache = 0;
-int gpgpu_mem_address_mask = 0;
-unsigned int recent_dram_util = 0;
-int gpgpu_cflog_interval = 0;
-unsigned int finished_trace = 0;
-unsigned g_next_request_uid = 1;
-int g_nthreads_issued;
-int g_total_cta_left;
-
+unsigned int gpgpu_dram_buswidth;
+unsigned int gpgpu_dram_burst_length;
+int   gpgpu_dram_sched_queue_size; 
+char *gpgpu_dram_timing_opt;
+bool  gpgpu_flush_cache;
+int   gpgpu_mem_address_mask;
+int   gpgpu_cflog_interval;
 
 void ptx_dump_regs( void *thd );
 unsigned ptx_kernel_program_size();
@@ -222,38 +219,38 @@ double l2_period = 1 / (2 MhZ);
 char * gpgpu_clock_domains;
 
 /* GPU uArch parameters */
-unsigned int gpu_n_mem = 8;
-unsigned int gpu_mem_n_bk = 4;
-unsigned int gpu_n_mem_per_ctrlr = 1;
-unsigned int gpu_n_shader = 8;
-int gpu_concentration = 1;
+unsigned int gpu_n_mem;
+unsigned int gpu_mem_n_bk;
+unsigned int gpu_n_mem_per_ctrlr;
+unsigned int gpu_n_shader;
+int gpu_concentration;
 int gpu_n_tpc = 8;
 unsigned int gpu_n_mshr_per_shader;
 unsigned int gpu_n_thread_per_shader = 128;
 unsigned int gpu_n_warp_per_shader;
 unsigned int gpu_n_mshr_per_thread = 1;
-bool gpgpu_reg_bankconflict = false;
-int gpgpu_operand_collector;
-int gpgpu_operand_collector_num_units = 4;
-unsigned int gpgpu_pre_mem_stages = 0;
-unsigned int gpgpu_no_divg_load = 0;
+bool gpgpu_reg_bankconflict;
+bool gpgpu_operand_collector;
+int gpgpu_operand_collector_num_units;
+unsigned int gpgpu_pre_mem_stages;
+bool gpgpu_no_divg_load;
 char *gpgpu_dwf_hw_opt;
-unsigned int gpgpu_thread_swizzling = 0;
-unsigned int gpgpu_strict_simd_wrbk = 0;
-int pdom_sched_type = 0;
+bool gpgpu_thread_swizzling;
+bool gpgpu_strict_simd_wrbk;
+int pdom_sched_type;
 int n_pdom_sc_orig_stat = 0; //the selected pdom schedular is used 
 int n_pdom_sc_single_stat = 0; //only a single warp is ready to go in that cycle.  
 int *num_warps_issuable;
 int *num_warps_issuable_pershader;
-int gpgpu_cuda_sim = 1;
-int gpgpu_spread_blocks_across_cores = 1;
+bool gpgpu_cuda_sim;
+bool gpgpu_spread_blocks_across_cores;
 shader_core_ctx_t **sc;
 dram_t **dram;
 unsigned int common_clock = 0;
 unsigned int more_thread = 1;
 unsigned int warp_conflict_at_writeback = 0;
 unsigned int gpgpu_commit_pc_beyond_two = 0;
-int gpgpu_cache_wt_through = 0;
+bool gpgpu_cache_wt_through;
 
 //memory access classification
 int gpgpu_n_mem_read_local = 0;
@@ -366,7 +363,7 @@ void gpu_reg_options(option_parser_t opp)
                 "Check for bank conflict in the pipeline",
                 "0");
 
-   option_parser_register(opp, "-gpgpu_dwf_regbk", OPT_BOOL, (int*)&gpgpu_dwf_regbk, 
+   option_parser_register(opp, "-gpgpu_dwf_regbk", OPT_BOOL, &gpgpu_dwf_regbk, 
                 "Have dwf scheduler to avoid bank conflict",
                 "1");
 
@@ -411,7 +408,7 @@ void gpu_reg_options(option_parser_t opp)
                 "default = 0 pre-memory pipeline stages",
                 "0");
 
-   option_parser_register(opp, "-gpgpu_no_divg_load", OPT_BOOL, (int*)&gpgpu_no_divg_load, 
+   option_parser_register(opp, "-gpgpu_no_divg_load", OPT_BOOL, &gpgpu_no_divg_load, 
                 "Don't allow divergence on load",
                 "0");
 
@@ -419,11 +416,11 @@ void gpu_reg_options(option_parser_t opp)
                   "dynamic warp formation hw config, i.e., {<#LUT_entries>:<associativity>|none}",
                   "32:2");
 
-   option_parser_register(opp, "-gpgpu_thread_swizzling", OPT_BOOL, (int*)&gpgpu_thread_swizzling, 
+   option_parser_register(opp, "-gpgpu_thread_swizzling", OPT_BOOL, &gpgpu_thread_swizzling, 
                 "Thread Swizzling (1=on, 0=off)",
                 "0");
 
-   option_parser_register(opp, "-gpgpu_strict_simd_wrbk", OPT_BOOL, (int*)&gpgpu_strict_simd_wrbk, 
+   option_parser_register(opp, "-gpgpu_strict_simd_wrbk", OPT_BOOL, &gpgpu_strict_simd_wrbk, 
                 "Applying Strick SIMD WriteBack Stage (1=on, 0=off)",
                 "0");
 
@@ -677,8 +674,7 @@ unsigned int run_gpu_sim(int grid_num)
    not_completed = 1;
    mem_busy = 1;
    icnt2mem_busy = 1;
-   finished_trace = 0;
-   g_next_request_uid = 1;
+   g_next_mf_request_uid = 1;
    more_thread = 1;
    gpu_sim_insn = 0;
    gpu_sim_insn_no_ld_const = 0;
@@ -1025,7 +1021,7 @@ unsigned char fq_push(unsigned long long int addr, int bsize, unsigned char writ
    mem_fetch_t *mf;
 
    mf = (mem_fetch_t*) calloc(1,sizeof(mem_fetch_t));
-   mf->request_uid = g_next_request_uid++;
+   mf->request_uid = g_next_mf_request_uid++;
    mf->addr = addr;
    mf->nbytes_L1 = bsize;
    mf->sid = sid;
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index a69a3ef..4fa0aaa 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -109,9 +109,8 @@ extern unsigned int L1_const_miss;
 extern unsigned int L1_write_hit_on_miss;
 extern unsigned int L1_writeback;
 extern unsigned int L1_const_miss;
-extern unsigned int finished_trace;
 extern bool gpgpu_perfect_mem;
-extern int gpgpu_no_dl1;
+extern bool gpgpu_no_dl1;
 extern char *gpgpu_cache_texl1_opt;
 extern char *gpgpu_cache_constl1_opt;
 extern char *gpgpu_cache_dl1_opt;
@@ -137,24 +136,24 @@ extern unsigned long long  gpu_sim_insn_last_update;
 extern unsigned long long  gpu_completed_thread;
 extern class shader_core_ctx **sc;
 extern unsigned int gpgpu_pre_mem_stages;
-extern unsigned int gpgpu_no_divg_load;
-extern unsigned int gpgpu_thread_swizzling;
-extern unsigned int gpgpu_strict_simd_wrbk;
+extern bool gpgpu_no_divg_load;
+extern bool gpgpu_thread_swizzling;
+extern bool gpgpu_strict_simd_wrbk;
 extern unsigned int warp_conflict_at_writeback;
 extern unsigned int gpgpu_commit_pc_beyond_two;
-extern int gpgpu_spread_blocks_across_cores;
+extern bool gpgpu_spread_blocks_across_cores;
 extern int gpgpu_cflog_interval;
 extern unsigned int gpu_stall_by_MSHRwb;
 extern unsigned int gpu_stall_shd_mem;
 extern unsigned int gpu_stall_sh2icnt;
-extern int gpgpu_operand_collector;
+extern bool gpgpu_operand_collector;
 extern int gpgpu_operand_collector_num_units;
 extern int gpu_runtime_stat_flag;
 extern unsigned int *max_return_queue_length;
 extern int gpgpu_partial_write_mask;
 extern int gpgpu_n_mem_write_local;
 extern int gpgpu_n_mem_write_global;
-extern int gpgpu_cache_wt_through;
+extern bool gpgpu_cache_wt_through;
 extern double core_freq;
 extern double icnt_freq;
 extern double dram_freq;
@@ -162,14 +161,16 @@ extern double l2_freq;
 extern int pdom_sched_type;
 extern int n_pdom_sc_orig_stat;
 extern int n_pdom_sc_single_stat;
-extern int gpgpu_cuda_sim;
+extern bool gpgpu_cuda_sim;
 extern int gpgpu_mem_address_mask;
 extern bool g_interactive_debugger_enabled;
 extern unsigned int gpu_n_mem_per_ctrlr;
-extern unsigned int recent_dram_util;
 extern unsigned int **concurrent_row_access; //concurrent_row_access[dram chip id][bank id]
 extern unsigned long long  gpu_tot_sim_insn;
 extern unsigned int gpgpu_n_sent_writes;
 extern unsigned int gpgpu_n_processed_writes;
+extern int gpgpu_simd_model;
+extern unsigned int gpu_mem_n_bk;
+extern unsigned g_next_mf_request_uid;
 
 #endif
diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc
index e9f4780..f27c940 100644
--- a/src/gpgpu-sim/l2cache.cc
+++ b/src/gpgpu-sim/l2cache.cc
@@ -51,7 +51,6 @@ extern int gpgpu_dram_sched_queue_size;
 extern unsigned made_write_mfs;
 extern unsigned freed_L1write_mfs;
 extern unsigned freed_L2write_mfs;
-extern unsigned g_next_request_uid;
 
 void memlatstat_icnt2sh_push(mem_fetch_t *mf);
 void memlatstat_dram_access(mem_fetch_t *mf, unsigned dram_id, unsigned bank);
@@ -60,8 +59,8 @@ unsigned memlatstat_done(mem_fetch_t *mf);
 
 // option
 char *gpgpu_L2_queue_config;
-int gpgpu_l2_readoverwrite = 0;
-int l2_ideal = 0;
+bool gpgpu_l2_readoverwrite;
+bool l2_ideal;
 
 void L2c_options(option_parser_t opp)
 {
@@ -715,7 +714,7 @@ unsigned char L2c_write_back(unsigned long long int addr, int bsize, int dram_id
 
    mf = (mem_fetch_t*) malloc(sizeof(mem_fetch_t));
    made_write_mfs++;
-   mf->request_uid = g_next_request_uid++;
+   mf->request_uid = g_next_mf_request_uid++;
    mf->addr = addr;
    mf->nbytes_L1 = bsize + READ_PACKET_SIZE;
    mf->txbytes_L1 = 0;
diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h
index d245408..6566dd7 100644
--- a/src/gpgpu-sim/l2cache.h
+++ b/src/gpgpu-sim/l2cache.h
@@ -50,4 +50,4 @@ extern unsigned L2_write_miss;
 extern unsigned L2_write_hit;
 extern unsigned L2_read_hit;
 extern unsigned L2_read_miss;
-extern int gpgpu_l2_readoverwrite;
+extern bool gpgpu_l2_readoverwrite;
diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc
index 19cc76b..625e54f 100644
--- a/src/gpgpu-sim/mem_latency_stat.cc
+++ b/src/gpgpu-sim/mem_latency_stat.cc
@@ -73,18 +73,13 @@
 #include "stat-tool.h"
 #include "../cuda-sim/ptx-stats.h"
 #include "visualizer.h"
+#include "dram.h"
 
 #include <string.h>
 #include <stdlib.h>
 #include <stdio.h>
 
-extern unsigned int gpu_n_mem;
-extern unsigned int gpu_n_shader;
-extern int gpgpu_dram_sched_queue_size;
-extern int gpgpu_dram_scheduler;
-extern unsigned int gpu_mem_n_bk;
-
-bool gpgpu_memlatency_stat = false;
+bool gpgpu_memlatency_stat;
 
 unsigned max_mrq_latency;
 unsigned max_dq_latency;
diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h
index 3b266ef..655cf04 100644
--- a/src/gpgpu-sim/mem_latency_stat.h
+++ b/src/gpgpu-sim/mem_latency_stat.h
@@ -68,8 +68,6 @@
 #ifndef MEM_LATENCY_STAT_H
 #define MEM_LATENCY_STAT_H
 
-extern int gpgpu_dram_scheduler;
-extern unsigned int gpu_mem_n_bk;
 extern bool gpgpu_memlatency_stat;
 
 extern unsigned max_mrq_latency;
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index bba2b8b..057e374 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -82,6 +82,7 @@
 #include "mem_latency_stat.h"
 #include "visualizer.h"
 #include <string.h>
+#include <limits.h>
 
 #define PRIORITIZE_MSHR_OVER_WB 1
 #define MAX(a,b) (((a)>(b))?(a):(b))
@@ -113,9 +114,9 @@ unsigned warp_size = 4;
 int pipe_simd_width;
 unsigned int *shader_cycle_distro;
 unsigned int g_waiting_at_barrier = 0;
-unsigned int gpgpu_shmem_size = 16384;
-unsigned int gpgpu_shader_registers = 8192;
-unsigned int gpgpu_shader_cta = 8;
+unsigned int gpgpu_shmem_size;
+unsigned int gpgpu_shader_registers;
+unsigned int gpgpu_shader_cta;
 unsigned int gpgpu_n_load_insn = 0;
 unsigned int gpgpu_n_store_insn = 0;
 unsigned int gpgpu_n_shmem_insn = 0;
@@ -123,24 +124,24 @@ unsigned int gpgpu_n_tex_insn = 0;
 unsigned int gpgpu_n_const_insn = 0;
 unsigned int gpgpu_n_param_insn = 0;
 unsigned int gpgpu_multi_unq_fetches = 0;
-int          gpgpu_shmem_bkconflict = 0;
+bool         gpgpu_shmem_bkconflict;
 unsigned int gpgpu_n_shmem_bkconflict = 0;
 int          gpgpu_n_shmem_bank = 16;
-int          gpgpu_cache_bkconflict = 0;
+bool         gpgpu_cache_bkconflict;
 unsigned int gpgpu_n_cache_bkconflict = 0;
 unsigned int gpgpu_n_cmem_portconflict = 0;
-int          gpgpu_n_cache_bank = 16;
-int          gpgpu_warpdistro_shader = -1;
-int          gpgpu_interwarp_mshr_merge = 0;
+int          gpgpu_n_cache_bank;
+int          gpgpu_warpdistro_shader;
+int          gpgpu_interwarp_mshr_merge;
 int          gpgpu_n_intrawarp_mshr_merge = 0;
 int          gpgpu_n_partial_writes = 0;
-int          gpgpu_shmem_port_per_bank = 4;
-int          gpgpu_cache_port_per_bank = 4;
-int          gpgpu_const_port_per_bank = 4;
-int          gpgpu_shmem_pipe_speedup = 2;
+int          gpgpu_shmem_port_per_bank;
+int          gpgpu_cache_port_per_bank;
+int          gpgpu_const_port_per_bank;
+int          gpgpu_shmem_pipe_speedup;
 unsigned int gpu_max_cta_per_shader = 8;
 unsigned int gpu_padded_cta_size = 32;
-int          gpgpu_local_mem_map = 1;
+int          gpgpu_local_mem_map;
 
 /////////////////////////////////////////////////////////////////////////////
 /*-------------------------------------------------------------------------*/
@@ -1649,10 +1650,10 @@ inline address_type translate_local_memaddr(address_type localaddr, shader_core_
 /////////////////////////////////////////////////////////////////////////////////////////
 // Register Bank Conflict Structures
 
-int gpgpu_reg_bank_conflict_model = 0;
+bool gpgpu_reg_bank_conflict_model;
 
 #define MAX_REG_BANKS 32
-unsigned int gpgpu_num_reg_banks=8; // this needs to be less than MAX_REG_BANKS
+unsigned int gpgpu_num_reg_banks; // this needs to be less than MAX_REG_BANKS
 
 #define MAX_BANK_CONFLICT 8 /* tex can have four source and four destination regs */
 
@@ -2075,7 +2076,7 @@ void shader_pre_memory( shader_core_ctx_t *shader,
    }
 }
 
-int gpgpu_coalesce_arch = 13;
+int gpgpu_coalesce_arch;
 
 enum memory_path {
    NO_MEM_PATH = 0,
@@ -3071,7 +3072,6 @@ void shader_writeback( shader_core_ctx_t *shader, unsigned int shader_number, in
          // thread completed if it is going to fetching beyond code boundry 
          if ( gpgpu_cuda_sim && ptx_thread_done(shader->thread[unlock_tid[i]].ptx_thd_info) ) {
 
-            finished_trace += 1;
             shader->not_completed -= 1;
             gpu_completed_thread += 1;
 
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 0a90225..ec1ae0b 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -67,7 +67,6 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <math.h>
-#include <limits.h>
 #include <assert.h>
 #include <map>
 #include <list>
@@ -911,15 +910,15 @@ extern int gpgpu_interwarp_mshr_merge;
 extern unsigned int gpgpu_shmem_size;
 extern unsigned int gpgpu_shader_registers;
 extern unsigned int gpgpu_shader_cta;
-extern int gpgpu_shmem_bkconflict;
-extern int gpgpu_cache_bkconflict;
+extern bool gpgpu_shmem_bkconflict;
+extern bool gpgpu_cache_bkconflict;
 extern int gpgpu_n_cache_bank;
 extern int pipe_simd_width;
 extern int gpgpu_shmem_port_per_bank;
 extern int gpgpu_cache_port_per_bank;
 extern int gpgpu_const_port_per_bank;
 extern int gpgpu_shmem_pipe_speedup;  
-extern int gpgpu_reg_bank_conflict_model;
+extern bool gpgpu_reg_bank_conflict_model;
 extern unsigned int gpgpu_num_reg_banks;
 extern unsigned int gpu_max_cta_per_shader;
 extern unsigned int gpu_padded_cta_size;
@@ -928,5 +927,6 @@ extern unsigned int n_regconflict_stall;
 extern int gpgpu_coalesce_arch;
 extern unsigned get_max_mshr_used(shader_core_ctx_t* shader);
 extern void mshr_return_from_mem(shader_core_ctx_t * shader, mshr_entry_t* mshr);
+void get_pdom_stack_top_info( unsigned sid, unsigned tid, unsigned *pc, unsigned *rpc );
 
 #endif /* SHADER_H */
diff --git a/src/gpgpu-sim/visualizer.cc b/src/gpgpu-sim/visualizer.cc
index 4ed8157..69c4452 100644
--- a/src/gpgpu-sim/visualizer.cc
+++ b/src/gpgpu-sim/visualizer.cc
@@ -76,9 +76,9 @@
 static void time_vector_print_interval2file(FILE *outfile);
 static void time_vector_print_interval2gzfile(gzFile outfile);
 
-int g_visualizer_enabled = 1;
-char *g_visualizer_filename = NULL;
-int g_visualizer_zlevel = 6;
+bool g_visualizer_enabled;
+char *g_visualizer_filename;
+int g_visualizer_zlevel;
 
 void visualizer_options(option_parser_t opp)
 {