diff options
| author | Inderpreet Singh <[email protected]> | 2012-02-26 04:11:23 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:19:04 -0700 |
| commit | 609ebad6b15d4cd08e5a34579a73433772bf0e9f (patch) | |
| tree | 657aa7bf4665fc31765551436891682935f98900 /src | |
| parent | 928f6d330516f03bdbecd52350bf1b9fb9fcf534 (diff) | |
Turned ROP and DRAM latency/delays into options
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11522]
Diffstat (limited to 'src')
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 6 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.h | 3 | ||||
| -rw-r--r-- | src/gpgpu-sim/l2cache.cc | 4 |
3 files changed, 11 insertions, 2 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index bd77c7b..0671780 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -125,6 +125,12 @@ void memory_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_dram_timing_opt", OPT_CSTR, &gpgpu_dram_timing_opt, "DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR}", "4:2:8:12:21:13:34:9:4:5:13"); + option_parser_register(opp, "-rop_latency", OPT_UINT32, &rop_latency, + "ROP queue latency (default 115)", + "115"); + option_parser_register(opp, "-dram_latency", OPT_UINT32, &dram_latency, + "DRAM latency (default 100)", + "100"); m_address_mapping.addrdec_setoption(opp); } diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 7c14594..31def4b 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -97,6 +97,9 @@ struct memory_config { unsigned m_n_mem; unsigned gpu_n_mem_per_ctrlr; + unsigned rop_latency; + unsigned dram_latency; + // DRAM parameters unsigned tCCD; //column to column delay unsigned tRRD; //minimal time required between activation of rows in different banks diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index 6a39b42..e57717f 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -262,7 +262,7 @@ void memory_partition_unit::push( mem_fetch* req, unsigned long long cycle ) } else { rop_delay_t r; r.req = req; - r.ready_cycle = cycle + 115; // Add 115*4=460 delay cycles + r.ready_cycle = cycle + m_config->rop_latency; m_rop.push(r); req->set_status(IN_PARTITION_ROP_DELAY,gpu_sim_cycle+gpu_tot_sim_cycle); } @@ -322,7 +322,7 @@ void memory_partition_unit::dram_cycle() mem_fetch *mf = m_L2_dram_queue->pop(); dram_delay_t d; d.req = mf; - d.ready_cycle = gpu_sim_cycle+gpu_tot_sim_cycle + 200; + d.ready_cycle = gpu_sim_cycle+gpu_tot_sim_cycle + m_config->dram_latency; m_dram_latency_queue.push(d); mf->set_status(IN_PARTITION_DRAM_LATENCY_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); } |