diff options
| author | Negar <[email protected]> | 2017-11-12 19:03:27 -0800 |
|---|---|---|
| committer | negargoli93 <[email protected]> | 2017-11-12 19:34:51 -0800 |
| commit | 7c9b838bca837a3ccea5ea30f53c1cbd8e35252c (patch) | |
| tree | d3f41701c2e81c91daf1f5a5d3a3269455a31b67 /src | |
| parent | 8735428754d1bb944400922982f41f867f2f9b9c (diff) | |
Fix latency bug
Diffstat (limited to 'src')
| -rw-r--r-- | src/cuda-sim/cuda-sim.cc | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index b5b79e7..54d8796 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -69,9 +69,9 @@ unsigned cdp_latency[5]; void ptx_opcocde_latency_options (option_parser_t opp) { option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, - "Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>" - "Default 1,1,19,25,145,1", - "1,1,19,25,145,1"); + "Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Presicion,BSMAD_lane_width>" + "Default 1,1,19,25,145,1,4", + "1,1,19,25,145,1,4"); option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp, "Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>" "Default 1,1,1,1,30", @@ -81,8 +81,8 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Default 8,8,8,8,335", "8,8,8,8,335"); option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, - "Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>" - "Default 1,1,4,4,32,1", + "Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Precision,BSMAD_lane_width>" + "Default 1,1,4,4,32,1,1", "1,1,4,4,32,1"); option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp, "Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>" @@ -589,10 +589,14 @@ void ptx_instruction::set_bar_type() void ptx_instruction::set_opcode_and_latency() { - unsigned int_latency[6]; + unsigned int_latency[5]; + unsigned int_precision; + unsigned int_lane_width; unsigned fp_latency[5]; unsigned dp_latency[5]; - unsigned int_init[6]; + unsigned int_init[5]; + unsigned int_init_precision; + unsigned int_init_lane_width; unsigned fp_init[5]; unsigned dp_init[5]; /* @@ -603,18 +607,18 @@ void ptx_instruction::set_opcode_and_latency() * [4] DIV * [5] BSMAD */ - sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u", + sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u,%u", &int_latency[0],&int_latency[1],&int_latency[2], - &int_latency[3],&int_latency[4],&int_latency[5]); + &int_latency[3],&int_latency[4],&int_precision,&int_lane_width); sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u", &fp_latency[0],&fp_latency[1],&fp_latency[2], &fp_latency[3],&fp_latency[4]); sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u", &dp_latency[0],&dp_latency[1],&dp_latency[2], &dp_latency[3],&dp_latency[4]); - sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u", + sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u, %u", &int_init[0],&int_init[1],&int_init[2], - &int_init[3],&int_init[4],&int_init[5]); + &int_init[3],&int_init[4],&int_init_precision,&int_init_lane_width); sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u", &fp_init[0],&fp_init[1],&fp_init[2], &fp_init[3],&fp_init[4]); @@ -789,8 +793,8 @@ void ptx_instruction::set_opcode_and_latency() op = SFU_OP; break; case BSMAD_OP: - latency = int_latency[5]; - initiation_interval = int_init[5]; + latency = int_precision/int_lane_width; + initiation_interval = int_init_precision/int_init_lane_width; break; case SHFL_OP: latency = 32; |