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authortgrogers <[email protected]>2018-09-11 21:46:34 -0400
committertgrogers <[email protected]>2018-09-11 21:46:34 -0400
commit879023148950e7322b5aa85dd98a60b3a069cd44 (patch)
tree1523d02ee947078f89506e44516ebc7fc94c9bb9 /src
parent46817ba62f475ba1202c31a8939ea1a1de81a410 (diff)
parentf4116831d7354c80dcd3cf857fcb5be7b001d70f (diff)
Merge branch 'dev-purdue-integration' of https://github.rcac.purdue.edu/TimRogersGroup/gpgpu-sim_distribution into dev-purdue-integration
Diffstat (limited to 'src')
-rw-r--r--src/abstract_hardware_model.h1
-rw-r--r--src/cuda-sim/cuda-sim.cc1
-rw-r--r--src/cuda-sim/ptx_ir.cc1
-rw-r--r--src/gpgpu-sim/shader.cc2
4 files changed, 4 insertions, 1 deletions
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 1b764e2..6df7b89 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -664,6 +664,7 @@ enum cache_operator_type {
CACHE_ALL, // .ca
CACHE_LAST_USE, // .lu
CACHE_VOLATILE, // .cv
+ CACHE_L1, // .nc
// loads and stores
CACHE_STREAMING, // .cs
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 9246613..93bbc1d 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -898,6 +898,7 @@ void ptx_instruction::pre_decode()
switch( m_cache_option ) {
case CA_OPTION: cache_op = CACHE_ALL; break;
+ case NC_OPTION: cache_op = CACHE_L1; break;
case CG_OPTION: cache_op = CACHE_GLOBAL; break;
case CS_OPTION: cache_op = CACHE_STREAMING; break;
case LU_OPTION: cache_op = CACHE_LAST_USE; break;
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index ee36957..ba6d7ed 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -1211,6 +1211,7 @@ ptx_instruction::ptx_instruction( int opcode,
case EXTP_OPTION:
break;
case NC_OPTION:
+ m_cache_option = last_ptx_inst_option;
break;
case UP_OPTION:
case DOWN_OPTION:
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index d2f40a1..533c6f9 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1537,7 +1537,7 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea
bypassL1D = true;
} else if (inst.space.is_global()) { // global memory access
// skip L1 cache if the option is enabled
- if (m_core->get_config()->gmem_skip_L1D)
+ if (m_core->get_config()->gmem_skip_L1D && (CACHE_L1 != inst.cache_op))
bypassL1D = true;
}